On CMOS scaling and A/D-converter performance

The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency expressed by two commonly used figures-of-merit. The trends are used to estimate limits on the achievable ADC performance in nanometer CMOS technologies, with implications for LTE and WCDMA infrastructure applications particularly highlighted.

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