Behavioural Modelling and Simulation of Dual Cascaded PLL Based Frequency Synthesizer

In this paper, behavioural model of a dual cascaded phase locked loop (PLL) based frequency synthesizer is presented and the results are validated through SystemVision simulation using very high speed Integrated circuit hardware description language-analog mixed signal (VHDL-AMS). Dual cascaded PLL consists of a low jitter PLL employing a voltage controlled crystal oscillator (VCXO) followed by a wideband PLL employing normal voltage controlled oscillator (VCO). The advantage of using dual PLL in cascade configuration is that it provides very good performance in terms of low jitter as compared to a single PLL based frequency synthesizer. Simulation results obtained are in good agreement with the theoretical calculations.

[1]  J.M. Noras,et al.  Jitter minimization in Digital Transmission using dual phase locked loops , 2005, 2005 International Conference on Microelectronics.

[2]  J.-J. Charlot,et al.  VHDL-AMS modeling of a new PLL with an inverse sine phase detector (ISPD PLL) , 2002, Proceedings of the 2002 IEEE International Workshop on Behavioral Modeling and Simulation, 2002. BMAS 2002..

[3]  Eby G. Friedman,et al.  Design and simulation of Fractional-N PLL frequency synthesizers , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[4]  Ernst Christen,et al.  Vhdl-ams---a hardware description language for analog and mixed-signal applications , 1999 .

[5]  Peter R. Wilson,et al.  Behavioural modeling and simulation of a switched-current phase locked loop , 2005, BMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005..

[6]  J.M. Noras,et al.  Simulation technique for noise and timing jitter in phase locked loop , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

[7]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[8]  Peter J. Ashenden,et al.  The System Designer's Guide to VHDL-AMS , 2002 .

[9]  Roland E. Best.  Phase-locked loops : design, simulation, and applications , 2003 .

[10]  Alex Doboli,et al.  Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Dan H. Wolaver,et al.  Phase-Locked Loop Circuit Design , 1991 .