A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries

In this paper, we propose a design method for low-power self-timed combinational circuits and latches based on the 1-out-of-4 encoding method. We propose a 1-out-of-4 latch circuit using standard cell libraries in order to establish a semi-custom low-power self-timed design style. The energy consumption of the proposed circuits is about 18% average smaller than that of conventional dual-rail encoded circuits.

[1]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[2]  Jim D. Garside,et al.  A practical comparison of asynchronous design styles , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[3]  Jim D. Garside,et al.  SPA - a synthesisable Amulet core for smartcard applications , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[4]  Scott A. Brandt,et al.  NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[5]  Jens Sparsø,et al.  Principles of Asynchronous Circuit Design , 2001 .

[6]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.

[7]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[8]  Sachin S. Sapatnekar,et al.  Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing , 2007, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[9]  Luciano Lavagno,et al.  Handshake protocols for de-synchronization , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[10]  Steve Furber,et al.  Principles of Asynchronous Circuit Design: A Systems Perspective , 2010 .

[11]  Paul Day,et al.  Four-phase micropipeline latch control circuits , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[13]  S. Ohkawa,et al.  Analysis and characterization of device variations in an LSI chip using an integrated device matrix array , 2004 .

[14]  Alexandre Yakovlev,et al.  Design and analysis of dual-rail circuits for security applications , 2005, IEEE Transactions on Computers.

[15]  Takashi Nanya,et al.  TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[16]  William B. Toms,et al.  Synthesising heterogeneously encoded systems , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[17]  M. Nagata,et al.  A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits , 2005, IEEE Journal of Solid-State Circuits.

[18]  Kôki Abe,et al.  A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits , 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[19]  Takashi Nanya,et al.  Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs , 2001, ASP-DAC '01.