Intel Paragon XP/S - Architecture and Software Enviroment
暂无分享,去创建一个
The paper describes the hardware and software components of the Intel Paragon XP/S system, a distributed memory scalable multicomputer. The Paragon processing nodes, which are based on the Intel i860 XP RISC processor, are connected by a two-dimensional mesh with high bandwidth. This new interconnection network and the new operating system are the main differences between the Paragon and its predecessor, the iPSC/860 with its hypercube topology. The paper first gives an overview of the Paragon system architecture, the node architecture, the interconnection network, I/O interfaces, and peripherals. The second part outlines the Paragon OSF/1 operating system and the program development environment including programming models, compilers, application libraries, and tools for parallelization, debugging, and performance analysis.
[1] William J. Dally,et al. The torus routing chip , 2005, Distributed Computing.
[2] King Lee. On the Floating Point Performance of the I860TM Microprocessor , 1992, Int. J. High Speed Comput..
[3] Lionel M. Ni,et al. A survey of wormhole routing techniques in direct networks , 1993, Computer.
[4] Kai Li,et al. Shared virtual memory on loosely coupled multiprocessors , 1986 .
[5] Corporate Intel Corp.. i860 microprocessor family programmer's reference manual , 1992 .