Compilers, architectures and synthesis for embedded computing: retrospect and prospect

I am humbled and honored to be included in the ranks of my many distinguished predecessors who have been recognized with the W. Wallace McDowell Award. Beyond the personal dimension, it is especially satisfying to see the field of embedded computing being recognized through this award. Over the past fifteen years or so, the synergy of computer science and engineering, and electrical engineering principles, have led to major advances in this field. While embedded computing might be largely viewed as being based on electrical engineering innovation, I want to draw attention to the importance of computer science principles and practice, and their influence on the recent developments in this field. Notably, algorithms guided by complexity theory have provided an important basis at the foundational level. In particular, the judicious use of algorithms within the framework of compiler optimizations, have played a central role. Finally and perhaps most significantly, the notion of an instruction set architecture or isa, has provided a significant lens through which some of the interesting challenges in embedded computing have been tackled. With this as a backdrop, I will

[1]  B. Ramakrishna Rau The era of embedded computing , 2000, CASES '00.

[2]  Yale N. Patt,et al.  Critical issues regarding HPS, a high performance microarchitecture , 1985, MICRO 18.

[3]  E. C. Hall Reliability history of the Apollo guidance computer , 1972 .

[4]  George Radin,et al.  The 801 minicomputer , 1982, ASPLOS I.

[5]  Norman P. Jouppi,et al.  MIPS: a VLSI processor architecture , 1981 .

[6]  Henry Fuchs,et al.  An Expanded Multiprocessor Architecture for Video Graphics. , 1979, ISCA 1979.

[7]  Carlo H. Séquin,et al.  RISC I: a reduced instruction set VLSI computer , 1981, ISCA '98.

[8]  周天舒 Simulation program with integrated circuit emphasis (SPICE) model building method for size reduced process , 2010 .

[9]  Krishna V. Palem,et al.  Compiler optimization of embedded applications for an adaptive SoC architecture , 2006, CASES '06.

[10]  Daniele Vigo,et al.  Recent advances on two-dimensional bin packing problems , 2002, Discret. Appl. Math..

[11]  B. Ramakrishna Rau,et al.  PICO: Automatically Designing Custom Computers , 2002, Computer.

[12]  Amir Pnueli,et al.  Scheduling time-constrained instructions on pipelined processors , 2001, TOPL.

[13]  Krishna V. Palem,et al.  Compiler Optimizations for Adaptive EPIC Processors , 2001, EMSOFT.

[14]  Andrew S. Tanenbaum,et al.  Modern Operating Systems: Jumpstart Sampling Edition , 2008 .

[15]  Amir Pnueli,et al.  TimeC: A Time Constraint Language for ILP Processor Compilation , 2004, Constraints.

[16]  Krishna V. Palem,et al.  Adaptive explicitly parallel instruction computing , 2001 .

[17]  Scott A. Mahlke,et al.  Trimaran: An Infrastructure for Research in Instruction-Level Parallelism , 2004, LCPC.

[18]  B. Ramakrishna Rau,et al.  Architectural support for the efficient generation of code for horizontal architectures , 1982, ASPLOS I.

[19]  B. R. Rau,et al.  HPL-PD Architecture Specification:Version 1.1 , 2000 .

[20]  Microsystems Sun,et al.  Jini^ Architecture Specification Version 2.0 , 2003 .

[21]  David G. Hoag The history of Apollo on-board guidance, navigation, and control , 1976 .

[22]  John Cocke,et al.  A methodology for the real world , 1981 .

[23]  B. Ramakrishna Rau,et al.  Embedded Computing: New Directions in Architecture and Automation , 2000, HiPC.

[24]  Fred Kröger,et al.  Temporal Logic of Programs , 1987, EATCS Monographs on Theoretical Computer Science.

[25]  Ken Kennedy,et al.  Optimizing Compilers for Modern Architectures: A Dependence-based Approach , 2001 .

[26]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[27]  Frank O’Brien The Apollo Guidance Computer , 2010 .

[28]  L. Nagel,et al.  SPICE (Simulation Program with Integrated Circuit Emphasis) , 1973 .

[29]  Des Watson High-level languages and their compilers , 1989, International computer science series.

[30]  Henry Fuchs,et al.  An expandable multiprocessor architecture for video graphics (Preliminary Report) , 1979, ISCA '79.

[31]  Yale N. Patt,et al.  HPS, a new microarchitecture: rationale and introduction , 1985, MICRO 18.

[32]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[33]  Krishna Ssv. Palem On the Complexity of Precedence Constrained Scheduling , 1986 .

[34]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[35]  Robert L. Berger The undecidability of the domino problem , 1966 .

[36]  John Cocke,et al.  Register Allocation Via Coloring , 1981, Comput. Lang..

[37]  Sidney B. Gasser Program optimization , 1972, SICOSIM3.

[38]  James D. Meindl,et al.  Low power microelectronics: retrospect and prospect , 1995, Proc. IEEE.

[39]  B. Ramakrishna Rau,et al.  Instruction-level parallel processing: History, overview, and perspective , 2005, The Journal of Supercomputing.

[40]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[41]  Sidney B. Gasser Program optimization , 1972 .

[42]  B. Ramakrishna Rau,et al.  Iterative modulo scheduling: an algorithm for software pipelining loops , 1994, MICRO 27.

[43]  Krishna V. Palem,et al.  Scheduling time-critical instructions on RISC machines , 1989, TOPL.

[44]  Richard M. Karp,et al.  Combinatorics, complexity, and randomness , 1986, CACM.

[45]  Max B Aron ON A CLEAR DAY YOU CAN SEE FOREVER , 2002 .