Layer‐by‐Layer‐Assembled Reduced Graphene Oxide/Gold Nanoparticle Hybrid Double‐Floating‐Gate Structure for Low‐Voltage Flexible Flash Memory

Among the many possible device confi gurations of fl ash memory, fi eld-effect-transistor (FET)-based memory with a fl oating-gate architecture is considered to be a promising candidate towards the ultimate goal of fl ash memory due to its single-transistor realization, non-destructive read-out, and compatibility with complementary metal oxide–semiconductor (CMOS) devices. [ 1–5 ] Floating-gate FET memory with metal nanoparticles (NPs) embedded in the gate dielectric is a way to replace planar fl oating gates to meet the requirements of fast data access and high density for the next generation of fl ash memory. [ 6–12 ] However, poor charge-retention time induced by the thin tunneling dielectric layer is a drawback for NP fl oatinggate-memory devices. [ 13 ] Simply increasing the thickness of the tunneling dielectric layer would degrade the program/ erase speed and increase the power consumption. [ 12 ] On this regard, as an alternative approach, the double NP fl oating-gate structure has been proposed to achieve better retention properties. [ 13–15 ] In previous reports, double-NP fl oating gates have generally been made with the same materials. The retention time could be improved by preventing the trapped charge carriers leaking back to the channel through the energy barrier arising between the upper and lower fl oating gates. Nevertheless, most double-NP fl oating gates consisting of two layers of NPs fabricated by chemical synthesis or thermal evaporation could not form NP pairs in the vertical direction. Additionally, the double-NP fl oating-gate structure may result in a poor interface between the NPs and the dielectric layer, which would have an adverse impact on the overall device performance. Therefore, developing an appropriate upper-fl oating-gate material with the following properties is necessary for technological applications: i) a suitable work function to set up an energy barrier so a long retention time is obtained; ii) a large area to achieve an accurate spatial distribution on the lower fl oating gate; and iii) a fl attened surface to improve the interface quality between the double fl oating gate and the dielectric layer. As one of the thinnest materials ever known in the universe, graphene

[1]  S. V. Morozov,et al.  Dirac cones reshaped by interaction effects in suspended graphene , 2011 .

[2]  Kang-Deog Suh,et al.  Impact of floating gate dry etching on erase characteristics in NOR flash memory , 2002, IEEE Electron Device Letters.

[3]  Byung-Gook Park,et al.  Enhancement of Memory Performance Using Doubly Stacked Si-Nanocrystal Floating Gates Prepared by Ion Beam Sputtering in UHV , 2007, IEEE Transactions on Electron Devices.

[4]  Kian Ping Loh,et al.  Hydrothermal Dehydration for the “Green” Reduction of Exfoliated Graphene Oxide to Graphene and Demonstration of Tunable Optical Limiting Properties , 2009 .

[5]  F. Caruso,et al.  Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties. , 2007, Nature nanotechnology.

[6]  V. Roy,et al.  Low temperature processed bilayer dielectrics for low-voltage flexible saturated load inverters , 2011 .

[7]  P. Kim,et al.  Experimental observation of the quantum Hall effect and Berry's phase in graphene , 2005, Nature.

[8]  K. Novoselov,et al.  Detection of individual gas molecules adsorbed on graphene. , 2006, Nature materials.

[9]  Yong-Young Noh,et al.  Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory , 2010 .

[10]  Vellaisamy A. L. Roy,et al.  Nanoparticle size dependent threshold voltage shifts in organic memory transistors , 2011 .

[11]  Panagiotis Dimitrakis,et al.  Langmuir−Blodgett Film Deposition of Metallic Nanoparticles and Their Application to Electronic Memory Structures , 2003 .

[12]  Denis Flandre,et al.  Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories. , 2011, Nano letters.

[13]  Michael J. Natan,et al.  Kinetic Control of Interparticle Spacing in Au Colloid-Based Surfaces: Rational Nanometer-Scale Architecture , 1996 .

[14]  Jaegab Lee,et al.  Tunable Memory Characteristics of Nanostructured, Nonvolatile Charge Trap Memory Devices Based on a Binary Mixture of Metal Nanoparticles as a Charge Trapping Layer , 2009 .

[15]  Piero Olivo,et al.  Flash memory cells-an overview , 1997, Proc. IEEE.

[16]  R. Czerw,et al.  Substrate-interface interactions between carbon nanotubes and the supporting substrate , 2002 .

[17]  Jae Sung Sim,et al.  Multilevel Data Storage Memory Devices Based on the Controlled Capacitive Coupling of Trapped Electrons , 2011, Advanced materials.

[18]  Klaus Kern,et al.  Electronic transport properties of individual chemically reduced graphene oxide sheets. , 2007, Nano letters.

[19]  Hyoyoung Lee,et al.  Nonvolatile memory device using gold nanoparticles covalently bound to reduced graphene oxide. , 2011, ACS nano.

[20]  K. Novoselov,et al.  Giant intrinsic carrier mobilities in graphene and its bilayer. , 2007, Physical review letters.

[21]  Ju Hyun Park,et al.  Stable aqueous dispersion of reduced graphene nanosheets via non-covalent functionalization with conducting polymers and application in transparent electrodes. , 2011, Langmuir : the ACS journal of surfaces and colloids.

[22]  Shantang Liu,et al.  Evaporation-induced self-assembly of gold nanoparticles into a highly organized two-dimensional array , 2002 .

[23]  Byung-Seon Kong,et al.  Layer-by-layer assembly of graphene and gold nanoparticles by vacuum filtration and spontaneous reduction of gold ions. , 2009, Chemical communications.

[24]  Ji-Qing Xu,et al.  Modeling and simulation for the enhancement of electron storage in a stacked multilayer nanocrystallite silicon floating gate memory , 2007 .

[25]  C. N. Lau,et al.  Superior thermal conductivity of single-layer graphene. , 2008, Nano letters.

[26]  S. Bauer,et al.  Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays , 2009, Science.

[27]  G. Wallace,et al.  Processable aqueous dispersions of graphene nanosheets. , 2008, Nature nanotechnology.

[28]  Andre K. Geim,et al.  Electric Field Effect in Atomically Thin Carbon Films , 2004, Science.

[29]  H. Shin,et al.  Facile Method for rGO Field Effect Transistor: Selective Adsorption of rGO on SAM‐Treated Gold Electrode by Electrostatic Attraction , 2012, Advanced materials.

[30]  Su-Ting Han,et al.  Microcontact Printing of Ultrahigh Density Gold Nanoparticle Monolayer for Flexible Flash Memories , 2012, Advanced materials.

[31]  Jang-Sik Lee,et al.  Flexible organic transistor memory devices. , 2010, Nano letters.

[32]  Kian Ping Loh,et al.  High mobility, printable, and solution-processed graphene electronics. , 2010, Nano letters.

[33]  Seong-Wan Ryu,et al.  A thickness modulation effect of HfO2 interfacial layer between double-stacked Ag nanocrystals for nonvolatile memory device applications , 2007 .

[34]  Chuanbin Mao,et al.  Protein-Mediated Nanocrystal Assembly for Flash Memory Fabrication , 2007, IEEE Transactions on Electron Devices.

[35]  Jang‐Sik Lee Recent progress in gold nanoparticle-based non-volatile memory devices , 2010 .

[36]  Young-soo Park,et al.  Two Series Oxide Resistors Applicable to High Speed and High Density Nonvolatile Memory , 2007 .

[37]  Dong Uk Lee,et al.  Floating gated silicon-on-insulator nonvolatile memory devices with Au nanoparticles embedded in SiO1.3N insulators by digital sputtering method , 2007 .

[38]  Joong Tark Han,et al.  Highly tunable charge transport in layer-by-layer assembled graphene transistors. , 2012, ACS nano.

[39]  Kwang S. Kim,et al.  Ambipolar Memory Devices Based on Reduced Graphene Oxide and Nanoparticles , 2010, Advanced materials.

[40]  Shixin Wu,et al.  Electrochemical deposition of ZnO nanorods on transparent reduced graphene oxide electrodes for hybrid solar cells. , 2010, Small.

[41]  Kang L. Wang,et al.  Graphene flash memory. , 2011, ACS nano.

[42]  Jungdal Choi,et al.  Effects of floating-gate interference on NAND flash memory cell operation , 2002 .