AN EFFICIENT TEMPORAL PARTITIONING ALGORITHM TO MINIMIZECOMMUNICATION COST FOR RECONFIGURABLE COMPUTING SYSTEMS

In reconfigurable computing systems, full reconfigurable FPGA are evolving rapidly, due to their flexibility and high performance. In this paper, we focus on communication cost between partitions in order to develop an algorithm to solve temporal partitioning problems for full reconfigurable architecture. In fact, this algorithm optimizes the transfer of data required between design partitions. The proposed algorithm was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field

[1]  Evangeline F. Y. Young,et al.  Temporal logic replication for dynamically reconfigurable FPGA partitioning , 2002, ISPD '02.

[2]  João M. P. Cardoso.  On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures , 2003, IEEE Trans. Computers.

[3]  Evangeline F. Y. Young,et al.  Temporal logic replication for dynamically reconfigurable FPGA partitioning , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Henry L. Owen,et al.  Temporal Partitioning for Partially-Reconfigurable-Field-Programmable Gate , 1998, IPPS/SPDP Workshops.

[5]  Martin D. F. Wong,et al.  Network-flow-based multiway partitioning with area and pin constraints , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Michael William Newman,et al.  The Laplacian spectrum of graphs , 2001 .

[7]  Yao-Wen Chang,et al.  Generic ILP-based approaches for time-multiplexed FPGA partitioning , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Christophe Bobda,et al.  Introduction to reconfigurable computing - architectures, algorithms, and applications , 2010 .

[9]  B. Mohar.  THE LAPLACIAN SPECTRUM OF GRAPHS y , 1991 .

[10]  Steven Trimberger,et al.  Scheduling designs into a time-multiplexed FPGA , 1998, FPGA '98.

[11]  Jhing-Fa Wang,et al.  Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Mohamed Abid,et al.  An efficient list scheduling algorithm for time placement problem , 2007, Comput. Electr. Eng..

[13]  Martin D. F. Wong,et al.  Network flow based circuit partitioning for time-multiplexed FPGAs , 1998, ICCAD '98.

[14]  Martin D. F. Wong,et al.  Network flow based multi-way partitioning with area and pin constraints , 1997, ISPD '97.

[15]  Huiqun Liu,et al.  Network flow based circuit partitioning for time-multiplexed FPGAs , 1998, ICCAD 1998.

[16]  Abdellatif Mtibaa,et al.  Partitioning and scheduling technique for run time reconfigured systems , 2011, Int. J. Comput. Aided Eng. Technol..