论文信息 - High speed FIR filters for digital decimation

High speed FIR filters for digital decimation

This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in /spl Sigma//spl Delta/ A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk.

[1] K. Azadet,et al. Low-power equalizer architectures for high speed modems , 1998 .

[2] Peter Pirsch,et al. Architectures for digital signal processing , 1998 .

[3] H. V. Sorensen,et al. An overview of sigma-delta converters , 1996, IEEE Signal Process. Mag..

[4] Alan V. Oppenheim,et al. Signals & systems (2nd ed.) , 1996 .

[5] E. Hogenauer,et al. An economical class of digital filters for decimation and interpolation , 1981 .

[6] Yoshiaki Tadokoro,et al. A simple design of FIR filters with powers-of-two coefficients , 1988 .

[7] Valentino Liberali,et al. Efficient implementation of multiplier-free decimation filters for /spl Sigma//spl Delta/ A/D conversion , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[8] Max W. Hauser,et al. Principles of oversampling A/D conversion , 1991 .

[9] V. Liberali,et al. Cascade pseudomultibit noise shaping modulators , 1993 .

[10] S. Biyiksiz,et al. Multirate digital signal processing , 1985, Proceedings of the IEEE.