Physical-aware system-level design for tiled hierarchical chip multiprocessors

Tiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-efficient many-core computing systems. At the early stages of the design of a CMP, physical parameters are often ignored and postponed for later design stages. In this work, the importance of physical-aware system-level exploration is investigated, and a strategy for deriving chip floorplans is described. Additionally, wire planning of the on-chip interconnect is performed, as its topology and organization affect the physical layout of the system. Traditional algorithms for floorplanning and wire planning are customized to include physical constraints specific for tiled hierarchical architectures. Over-the-cell routing is used as one of the major area savings strategy. The combination of architectural exploration and physical planning is studied with an example and the impact of the physical aspects on the selection of architectural parameters is evaluated.

[1]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Chita R. Das,et al.  Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[3]  Martin D. F. Wong,et al.  Slicing tree is a complete floorplan representation , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  Saurabh Dighe,et al.  A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.

[5]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[6]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[7]  Martin D. F. Wong,et al.  A New Algorithm for Floorplan Design , 1986, 23rd ACM/IEEE Design Automation Conference.

[8]  Krishnan Srinivasan,et al.  A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[9]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[10]  Josep Carmona,et al.  Analytical Performance Modeling of Hierarchical Interconnect Fabrics , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[11]  Davide Bertozzi,et al.  Designing Network On-Chip Architectures in the Nanoscale Era , 2010 .

[12]  Martin D. F. Wong,et al.  Minimizing wire length in floorplanning , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Naveed A. Sherwani,et al.  Algorithms for VLSI Physical Design Automation , 1999, Springer US.

[14]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[15]  Ralph H. J. M. Otten,et al.  Automatic Floorplan Design , 1982, 19th Design Automation Conference.

[16]  Guowu Yang,et al.  Routability checking for three-dimensional architectures , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Ramon Canal,et al.  Power/Performance/Thermal Design-Space Exploration for Multicore Architectures , 2008, IEEE Transactions on Parallel and Distributed Systems.

[18]  F. Rubin,et al.  The Lee Path Connection Algorithm , 1974, IEEE Transactions on Computers.

[19]  Stefan Boettcher,et al.  Extremal Optimization: Methods derived from Co-Evolution , 1999, GECCO.

[20]  Evangeline F. Y. Young,et al.  Placement constraints in floorplan design , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Evangeline F. Y. Young,et al.  How good are slicing floorplans? , 1997, Integr..

[22]  William J. Dally,et al.  Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.

[23]  Giovanni De Micheli,et al.  Physical planning for on-chip multiprocessor networks and switch fabrics , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[24]  Tsung-Yi Ho,et al.  Bus-pin-aware bus-driven floorplanning , 2010, GLSVLSI '10.

[25]  Martin D. F. Wong,et al.  Floorplanning with alignment and performance constraints , 2002, DAC '02.

[26]  Igor L. Markov,et al.  Practical slicing and non-slicing block-packing without simulated annealing , 2004, GLSVLSI '04.