A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs

Embedded memories currently constitute a significant portion of the chip area for typical system-on-chip (SOC) designs. Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper proposes a shared parallel BISR scheme for random access memories (RAMs) in SOCs. The shared parallel BISR can test and repair multiple RAMs simultaneously. A global time-multiplexed built-in redundancy analyzer (TM-BIRA) is used to allocate redundancies of the RAMs under test and repair. We also design a 1500-compatible wrapper for chip-level control of the shared parallel BISR circuits. In comparison with the dedicated parallel BISR scheme (each memory has a self-contained BISR circuit), the proposed parallel BISR scheme can achieve 20% reduction of area cost by paying additional 0.005% test and repair time for serving 5 RAMs with spare rows and spare columns.

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