Implementation of a reconfigurable architecture of discrete wavelet packet transform with three types of multipliers on FPGA

This paper reports on the efficient implementations of a reconfigurable architecture of discrete wavelet packet transform (DWPT) with three types of multipliers on a field-programmable gate array (FPGA). The multipliers include the FPGA's internal multipliers, lookup table (LUT) based multipliers, and partial product multipliers (PPMs). Using two filters, a high-pass filter and a low-pass filter, which work concurrently at each level, speeds up the rate of data processing in the reported DWPT architecture. The results of implementations using these multipliers provide useful information that can help to select the best architecture for a particular application. The results also demonstrate that the DWPT architectures implemented using memory-based multipliers have a more stable operating frequency versus changes in the size of input data. Additionally, it is shown that PPMs can be used as an alternative to LUT-based multipliers as they occupy a smaller area on hardware platforms.