Active thread compaction for GPU path tracing

Modern GPUs like NVidia's Fermi internally operate in a SIMD manner by ganging multiple (32) scalar threads together into SIMD warps; if a warp's threads diverge, the warp serially executes both branches, temporarily disabling threads that are not on that path. In this paper, we explore and thoroughly analyze the concept of active thread compaction---i.e., the process of taking multiple partially-filled warps and compacting them to fewer but fully utilized warps---in the context of a CUDA path tracer. Our results show that this technique can indeed lead to significant improvements in SIMD utilization, and corresponding savings in the amount of work performed; however, they also show that certain inadequacies of today's hardware wipe out most of the achieved gains, leaving bottom-up speed-ups of a mere 12--16%. We believe our analysis of why this is the case will provide insight to other researchers experimenting with this technique in different contexts.