An efficient approach for via minimization in multi-layer VLSI/PCB routing

An efficient track permutation technique and a powerful Constrained Via Minimization (CVM) approach are proposed for multi-layer routing of VLSI chips and PCBs. Track permutation technique combined with existing channel routing algorithms can improve the routing results by permuting the tracks. For our multi-layer CVM approach, two procedures-Maximum-Difference Reduction procedure and Backtracking procedure are developed. In particular, the Maximum-Difference Reduction problem can be successfully converted to that of Minimum Clique Number Augmentation, and a polynomial-time heuristic algorithm is thereafter derived. The algorithms are evaluated by some famous routing examples using three and five layers. The obtained results, 38 percent of vias eliminated on an average, are very encouraging.