论文信息 - PLRU Cache Domino Effects

PLRU Cache Domino Effects

Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and StenstrAƒÂ¶m, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models.

Christoph Berg

[1] Per Stenström,et al. Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[2] Reinhard Wilhelm,et al. The influence of processor architecture on the design and the results of WCET tools , 2003, Proceedings of the IEEE.

[3] Thomas Lundqvist,et al. A WCET Analysis Method for Pipelined Microprocessors with Cache Memories , 2002 .

[4] Bernd Becker,et al. A Definition and Classification of Timing Anomalies , 2006, WCET.

[5] Jörn Schneider. Combined schedulability and WCET analysis for real-time operating systems , 2000 .