Application of alpha power law models to PLL design methodology

Designing, verifying and characterizing PLLs across process, voltage and temperature (PVT) variations takes large amounts of time, often resulting in empirical design approaches. Behavioral modeling of PLLs has been presented in literature and is also supported to varying degrees by EDA tools. However these approaches are either too simplistic or wanting in their ability to explore the PVT space. We present a behavioral model approach for phase locked loops using alpha power law behavioral models, which quickly allow the designer to examine design tradeoffs during early development phase. Self biased PLLs were used as a vehicle in this work. Behavioral models for each of the PLL sub blocks were developed using analog description language. The proposed approach provides a speed-up of more than 75/spl times/ with respect to SPICE with less than 10% error on a PLL in a 130 nm CMOS process at 900 MHz.

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