An Evaluation of Deeply Decoupled Cores

The trend towards larger structures and aggressive clock frequencies has been a fundamental driving force for modern microprocessor design. While one approach is to deeply pipeline any high delay structure, dependencies and critical loops have made it increasingly difcult to speed execution through extensive pipelining. One alternative is to remove larger structures from the critical path. We explore the ramications of stripping all but the most necessary functionality out of the processing core, leaving only a tiny -core. Although past studies have shown the possibility to build decoupled structures for some individual helper structures, the impact of streamlining all of these structures at the same time has not been explored. Along with describing the challenges in decoupling the helper engines, we focus on the performance, power consumption and thermal behavior of the -core architecture. We use a detailed performance, power and thermal modeling in our analysis. Our results indicate that the -core provides a 20% reduction in power over a conventional monolithic core, while providing comparable performance (1% improvement on average). By dynamically conguring the helper engines to different application phases, an additional 13% power savings can be attained with only an average 3% degradation in performance. Our experi