Compositional Techniques for Mixed Bottom-Up/Top-Down

Reduced Ordered Binary Decision Diagrams (ROBDDs) have traditionally been built in a bottom-up fashion, through the recursive use of Bryant''s apply procedure [4], or the ITE [2] procedure. With these methods, the intermediate peak memory utilization is often larger than the final ROBDD size. This peak memory requirement limits the complexity of the circuits which can be processed using ROBDDs. Recently it was shown in [9] that for a large number of applications, the peak memory requirement can be substantially reduced by a suitable combination of bottom-up (decomposition based) and top-down (composition based) approaches of building ROBDDs. This approach consists of selecting suitable decomposition points during the construction of the ROBDD using the apply procedure, followed by a symbolic composition to obtain the final ROBDD. In this paper, we focus on the composition process. We detail four heuristic algorithms for finding good composition orders, and compare their utility on a set of standard benchmark circuits. Our schemes offer a matrix of time-memory tradeoff points.

[1]  Robert K. Brayton,et al.  Combining Top-down and Bottom-up approaches for ROBDD , 1995 .

[2]  Rolf Drechsler,et al.  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.

[3]  R. Rudell Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[4]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[5]  Wolfgang Rosenstiel,et al.  Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.

[6]  Kenneth L. McMillan,et al.  Symbolic model checking: an approach to the state explosion problem , 1992 .

[7]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[8]  R. Bryant,et al.  Efficient implementation of a BDD package , 1990, 27th ACM/IEEE Design Automation Conference.

[9]  K. Karplus Using if-then-else DAGs for multi-level logic minimization , 1989 .

[10]  Jean Christophe Madre,et al.  Proving circuit correctness using formal comparison between expected and extracted behaviour , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[11]  Robert K. Brayton,et al.  Logic Verification Using BDDs in a Logic Synthesis Environ-ment , 1988 .

[12]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[13]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[14]  C. Y. Lee Representation of switching circuits by binary-decision programs , 1959 .