Magic's Circuit Extractor

We have implemented a fast hierarchical circuit extractor for the Magic VLSI layout system. The keys to its speed are a new algorithm based on corner-stitching , and its ability to extract cells incrementally. Because the extractor is incremental, typically only a few cells must be re-extracted when the layout changes. The extractor computes circuit connectivity and transistor dimensions, both internodal and substrate parasitic capacitance, and parasitic resistances. It is parameterized to work across a wide range of MOS technologies.

[1]  Anoop Gupta.  ACE: A Circuit Extractor , 1983, 20th Design Automation Conference Proceedings.

[2]  John K. Ousterhout.  Switch-Level Delay Models for Digital MOS VLSI , 1984, 21st Design Automation Conference Proceedings.

[3]  Gary M. Tarolli,et al.  Hierarchical Circuit Extraction with Detailed Parasitic Capacitance , 1983, 20th Design Automation Conference Proceedings.

[4]  John K. Ousterhout,et al.  Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Priscilla J. Fowler,et al.  Symbolic Parasitic Extractor for Circuit Simulation (SPECS) , 1983, 20th Design Automation Conference Proceedings.

[6]  B. J. Nelson,et al.  An integrated, technology-independent, high-performance artwork analyzer for VLSI circuit design , 1985 .

[7]  Steven Paul McCormick.  EXCL: A Circuit Extractor for IC Designs , 1984, 21st Design Automation Conference Proceedings.

[8]  Walter S. Scott,et al.  Magic: A VLSI Layout System , 1984, 21st Design Automation Conference Proceedings.

[9]  David A. Patterson,et al.  Architecture of SOAR: Smalltalk on a RISC , 1984, ISCA 1984.

[10]  Todd J. Wagner.  Hierarchical Layout Verification , 1985, IEEE Design & Test of Computers.