A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
暂无分享,去创建一个
Carlos González | Javier Resano | Daniel Mozos | Juan Antonio Clemente | J. A. Clemente | Carlos González | D. Mozos | J. Resano
[1] Juanjo Noguera,et al. Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling , 2004, TECS.
[2] Laszlo A. Belady,et al. A Study of Replacement Algorithms for Virtual-Storage Computer , 1966, IBM Syst. J..
[3] Francky Catthoor,et al. Reducing the reconfiguration overhead: a survey of techniques , 2007, ERSA.
[4] Carlos González,et al. A task graph execution manager for reconfigurable multi-tasking systems , 2010, Microprocess. Microsystems.
[5] Katherine Compton,et al. Scheduling Intervals for Reconfigurable Computing , 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.
[6] Diederik Verkest,et al. A reconfigurable manager for dynamically reconfigurable hardware , 2005, IEEE Design & Test of Computers.
[7] Nikil D. Dutt,et al. Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] Robert W. Brodersen,et al. A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[9] Francky Catthoor,et al. A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware [multimedia applications] , 2005, Design, Automation and Test in Europe.
[10] Diederik Verkest,et al. Run-Time Management of a MPSoC Containing FPGA Fabric Tiles , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[11] Vinita Vasudevan,et al. Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[12] Francky Catthoor,et al. Efficiently scheduling runtime reconfigurations , 2008, TODE.
[13] Peng Yang,et al. Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform , 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).
[14] Zexin Pan,et al. Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[15] Nikil D. Dutt,et al. Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Marco Platzner,et al. Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[17] Jari Nurmi,et al. A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[18] Carlos González,et al. A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.
[19] Zhiyuan Li,et al. Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation , 2002, FPGA '02.
[20] Fearghal Morgan,et al. Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux , 2007, 2007 International Conference on Field-Programmable Technology.
[21] Marco Platzner,et al. Online scheduling for block-partitioned reconfigurable devices , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[22] Rudy Lauwereins,et al. Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.