Improvement of compiled instruction set simulator by increasing flexibility and reducing compile time
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[1] Nikil D. Dutt,et al. Reducing compilation time overhead in compiled simulators , 2003, Proceedings 21st International Conference on Computer Design.
[2] Mendel Rosenblum,et al. Embra: fast and flexible machine simulation , 1996, SIGMETRICS '96.
[3] Luciano Lavagno,et al. Software performance estimation strategies in a system-level design tool , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).
[4] Heinrich Meyr,et al. Compiled Simulation of Programmable DSP Architectures , 1997, J. VLSI Signal Process..
[5] François Bodin,et al. Mastering startup costs in assembler-based compiled instruction-set simulation , 2002, Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures.
[6] Heinrich Meyr,et al. Compiled HW/SW co-simulation , 1996, DAC '96.
[7] Heinrich Meyr,et al. A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] G. D. Nagendra,et al. Simulation Bridge: a framework for multi-processor simulation , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).
[9] In-Cheol Park,et al. Timed compiled-code simulation of embedded software for performance analysis of SOC design , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[10] Nikil D. Dutt,et al. Instruction set compiled simulation: a technique for fast and flexible instruction set simulation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[11] James R. Larus,et al. Facile: a language and compiler for high-performance processor simulators , 2001, PLDI '01.
[12] G. Braun,et al. A universal technique for fast and flexible instruction-set architecture simulation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[13] Andreas Hoffmann,et al. A Novel Methodology for the Design of Application-Specific Instruction-Set Processors , 2005, Embedded Systems Handbook.
[14] H. Meyr,et al. Compiled HW/SW co-simulation , 1996, 33rd Design Automation Conference Proceedings, 1996.
[15] David Keppel,et al. Shade: a fast instruction-set simulator for execution profiling , 1994, SIGMETRICS.
[16] Jianwen Zhu,et al. An ultra-fast instruction set simulator , 2002, IEEE Trans. Very Large Scale Integr. Syst..