Flash Memory Array for Efficient Implementation of Deep Neural Networks

[1]  Jason Cong,et al.  Scaling for edge inference of deep neural networks , 2018 .

[2]  Bernabé Linares-Barranco,et al.  On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex , 2011, Front. Neurosci..

[3]  Arindam Ghosh,et al.  A high-performance MoS2 synaptic device with floating gate engineering for neuromorphic computing , 2019, 2D Materials.

[4]  J. Grollier,et al.  A ferroelectric memristor. , 2012, Nature materials.

[5]  Roberto Bez,et al.  Introduction to flash memory , 2003, Proc. IEEE.

[6]  Mohamed Medhat Gaber,et al.  Edge Machine Learning: Enabling Smart Internet of Things Applications , 2018, Big Data Cogn. Comput..

[7]  Onur Mutlu,et al.  Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[8]  Shih-Cheng Chen,et al.  Developments in nanocrystal memory , 2011 .

[9]  Andrew S. Cassidy,et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.

[10]  Denis C. Daly,et al.  Through the Looking Glass -- The 2017 Edition: Trends in Solid-State Circuits from ISSCC , 2017, IEEE Solid-State Circuits Magazine.

[11]  Alexander L. Wolf.  ACM's annual report for FY15 , 2016, Commun. ACM.

[12]  Yu Wang,et al.  PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[13]  H.-S. Philip Wong,et al.  In-memory computing with resistive switching devices , 2018, Nature Electronics.

[14]  Miao Hu,et al.  ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[15]  Vivienne Sze,et al.  Efficient Processing of Deep Neural Networks: A Tutorial and Survey , 2017, Proceedings of the IEEE.

[16]  S. Yuasa,et al.  A magnetic synapse: multilevel spin-torque memristor with perpendicular anisotropy , 2016, Scientific Reports.

[17]  Sparsh Mittal,et al.  A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors , 2016, ACM Comput. Surv..

[18]  Yakov Roizin,et al.  Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing , 2019, Nature Electronics.

[19]  C. Wright,et al.  Beyond von‐Neumann Computing with Nanoscale Phase‐Change Memory Devices , 2013 .

[20]  Geoffrey E. Hinton,et al.  Deep Learning , 2015, Nature.

[21]  M. Mitchell Waldrop,et al.  The chips are down for Moore’s law , 2016, Nature.

[22]  E. Stach.  Order in one dimension , 2018, Nature Materials.

[23]  Yu Wang,et al.  Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication , 2015, Journal of Computer Science and Technology.

[24]  Farnood Merrikh-Bayat,et al.  Training and operation of an integrated neuromorphic network based on metal-oxide memristors , 2014, Nature.

[25]  Joel Emer,et al.  Eyeriss: an Energy-efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks Accessed Terms of Use , 2022 .

[26]  Yachen Xiang,et al.  Efficient and Robust Spike-Driven Deep Convolutional Neural Networks Based on NOR Flash Computing Array , 2020, IEEE Transactions on Electron Devices.

[27]  Byung-Gook Park,et al.  3-D Floating-Gate Synapse Array With Spike-Time-Dependent Plasticity , 2018, IEEE Transactions on Electron Devices.

[28]  Jie Tang,et al.  Enabling Deep Learning on IoT Devices , 2017, Computer.

[29]  Xiaohui Liu,et al.  Hardware Implementation of Energy Efficient Deep Learning Neural Network Based on Nanoscale Flash Computing Array , 2019, Advanced Materials Technologies.