A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms

The design and implementation of today’s most advanced VLSI circuits and multi-layer printed circuit boards would not be possible without automated design tools that assist with the placement of components and the routing of connections between these components. In this work, we investigate how placement and routing can be implemented and accelerated using cloud computing resources. A parallel genetic algorithm approach is used to optimize component placement and the routing order supplied to a Lee’s algorithm maze router. A study of mutation rate, dominance rate, and population size is presented to suggest favorable parameter values for arbitrary-sized printed circuit board problems. The algorithm is then used to successfully design a Microchip PIC18 breakout board and Micrel Ethernet Switch. Performance results demonstrate that a 50X runtime performance improvement over a serial approach is achievable using 64 cloud computing cores. The results further suggest that significantly greater performance could be achieved by requesting additional cloud computing resources for additional cost. It is our hope that this work will serve as a framework for future efforts to improve parallel placement and routing algorithms using cloud computing

[1]  Jens Lienig,et al.  A parallel genetic algorithm for performance-driven VLSI routing , 1997, IEEE Trans. Evol. Comput..

[2]  Chak-Kuen Wong,et al.  New algorithms for the rectilinear Steiner tree problem , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Takeshi Yoshimura,et al.  Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  V. Roychowdhury,et al.  Segmented channel routing , 1990, 27th ACM/IEEE Design Automation Conference.

[5]  Majid Sarrafzadeh.  Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  N. Quinn,et al.  A forced directed component placement procedure for printed circuit boards , 1979 .

[7]  Joseph L. Ganley,et al.  Routing a multi-terminal critical net: Steiner tree construction in the presence of obstacles , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[8]  Jens Lienig,et al.  A new genetic algorithm for the channel routing problem , 1994, Proceedings of 7th International Conference on VLSI Design.

[9]  Robert K. Brayton,et al.  A force-directed macro-cell placer , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[10]  Brian W. Kernighan,et al.  A proper model for the partitioning of electrical circuits , 1972, DAC '72.

[11]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Randy H. Katz,et al.  Above the Clouds: A Berkeley View of Cloud Computing , 2009 .

[13]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[14]  Richard M. Karp,et al.  Reducibility Among Combinatorial Problems , 1972, 50 Years of Integer Programming.

[15]  Wilm E. Donath.  Complexity Theory and Design Automation , 1980, 17th Design Automation Conference.

[16]  Sartaj Sahni,et al.  The Complexity of Design Automation Problems , 1980, 17th Design Automation Conference.

[17]  Pinaki Mazumder,et al.  VLSI cell placement techniques , 1991, CSUR.

[18]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[19]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[20]  Sachin S. Sapatnekar,et al.  A survey on multi-net global routing for integrated circuits , 2001, Integr..

[21]  Thomas G. Szymanski.  Dogleg Channel Routing is NP-Complete , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Lalit M. Patnaik,et al.  Adaptive probabilities of crossover and mutation in genetic algorithms , 1994, IEEE Trans. Syst. Man Cybern..

[23]  Oliver Vornberger,et al.  An Adaptive Parallel Genetic Algorithm for VLSI-Layout Optimization , 1996, PPSN.

[24]  Alex Zelikovsky,et al.  Improved Steiner tree approximation in graphs , 2000, SODA '00.

[25]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[26]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.