New architectures for deep submicron MOSFETs

In scaling down MOSFETs to deep submicron gate lengths, the basic limitations are twofold. The first one is from a physical origin and related to short channel effects ( seE ) and hot carrier degradation. The second limitation is technology related and more specifically to dopant redistribution and lithography. In this paper the classical device architectures will be compared with respect to their short channel behaviour and in addition a new device architecture will be presented which circumvents the above mentioned limitations.