Rapid Prototyping of Quaternion Multiplier: From Matrix Notation to FPGA-Based Circuits

In recent years, hypercomplex numbers called quaternions attract attention of many researchers of the fields of digital signal processing (DSP), control, computer graphics, telecommunications, and others. By using hypercomplex arithmetic, known algorithms can be improved or extended to 4 dimensions so as to find new applications (Alexiadis & Sergiadis, 2009; Chan et al., 2008; Denis et al., 2007; Ell & Sangwine, 2007; Karney, 2007; Marion et al., 2010; Parfieniuk & Petrovsky, 2010a; Seberry et al., 2008; Took M Tsui et al., 2008; Zhou et al., 2007). Current research is mainly focused on theoretical development of quaternion-based algorithms, but one can expect that, in the course of time, engineers and scientists will implement them in hardware, and thus will need building blocks, design insights, methodologies, and tools. In known algorithms that use hypercomplex arithmetic, the key operation is quaternion multiplication, whose efficiency and accuracy obviously determines the same properties of the whole computational scheme of a filter or transform. Even though the operation has been thoroughly investigated from a mathematical point of view (Howell & Lafon, 1975), rather little is known about the practical aspects of implementing it in hardware as a dedicated digital circuit. To the best of our knowledge, only two research groups reported development of fixed-point quaternion multipliers. In (Delosme & Hsiao, 1990; Hsiao & Delosme, 1996; Hsiao et al., 2000; Parfieniuk & Petrovsky, 2010b; Petrovsky et al., 2001; Verenik et al., 2007), they considered various approaches to computing constant-coefficient multiplication using only binary shifts and additions: CORDIC, lifting, and Distributed Arithmetic (DA), but there is no review of the developed computational schemes, which would allow them to be compared and would inspire further research. The present chapter has two aims. The first one is to briefly review known facts and achievements related to quaternion multipliers and, by presenting a novel CORDIC-Inside-Lifting architecture, to show that there is much to do in this field. The second aim is to present our methodology and design results related to rapid prototyping of different multiplier schemes using a Xilinx Virtex FPGA device. The chapter contents should be useful to persons interested in implementing hypercomplex computations, as it should allow readers Rapid Prototyping of Quaternion Multiplier: From Matrix Notation to FPGA-Based Circuits 11