On high-speed computing with a programmable linear array

It has been observed by many researchers that systolic arrays are very suitable for certain high-speed computations. Using a formal methodology, we present a design for a single simple programmable linear systolic array capable of solving large numbers of problems drawn from a variety of applications. The methodology is applicable to problems solvable by sequential algorithms that can be specified as nested for-loops of arbitrary depth. The algorithms of this form that can be computed on the array presented in this paper include 25 algorithms dealing with signal and image processing, algebraic computations, matrix arithmetic, pattern matching, database operations, sorting, and transitive closure. Assuming bounded I/O, for 18 of those algorithms the time and storage complexities are optimal, and therefore no improvement can be expected by using dedicated special-purpose linear systolic arrays designed for individual algorithms. We also describe another design which, using a sufficient large local memory and allowing data to be preloaded and unloaded, has an optimal processor/time product.

[1]  Chuan-Lin Wu,et al.  Interconnection Networks for Parallel and Distributed Processing , 1984 .

[2]  H. T. Kung,et al.  Direct VLSI Implementation of Combinatorial Algorithms , 1979 .

[3]  PEIZONG LEE,et al.  Synthesizing Linear Array Algorithms from Nested For Loop Algorithms , 2015, IEEE Trans. Computers.

[4]  D.I. Moldovan,et al.  On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[5]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[6]  Marina C. Chen,et al.  The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI , 1988, IEEE Trans. Computers.

[7]  PeiZong Lee,et al.  SYSDES: A Systolic Array Automation Design System , 1989, PPSC.

[8]  H. T. Kung,et al.  Wafer-scale integration and two-level pipelined implementations of systolic arrays , 1984, J. Parallel Distributed Comput..

[9]  I. V. Ramakrishnan,et al.  Mapping Homogeneous Graphs on Linear Arrays , 1986, IEEE Transactions on Computers.

[10]  H. T. Kung Systolic algorithms for the CMU warp processor , 1984 .

[11]  P. Quinton Automatic synthesis of systolic arrays from uniform recurrent equations , 1984, ISCA 1984.

[12]  Dan I. Moldovan,et al.  Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays , 1986, IEEE Transactions on Computers.

[13]  H. T. Kung Use of VLSI in algebraic computation: Some suggestions , 1981, SYMSAC '81.

[14]  Richard W. Heuft,et al.  Improved Time and Parallel Processor Bounds for Fortran-Like Loops , 1982, IEEE Transactions on Computers.

[15]  H. T. Kung Why systolic architectures? , 1982, Computer.

[16]  H. T. Kung,et al.  The Design of Special-Purpose VLSI Chips , 1980, Computer.

[17]  Kai Hwang,et al.  Partitioned Matrix Algorithms for VLSI Arithmetic Systems , 1982, IEEE Transactions on Computers.

[18]  H. T. Kung,et al.  The Warp Computer: Architecture, Implementation, and Performance , 1987, IEEE Transactions on Computers.

[19]  Utpal Banerjee,et al.  Time and Parallel Processor Bounds for Fortran-Like Loops , 1979, IEEE Transactions on Computers.

[20]  H. T. Kung,et al.  Systolic (VLSI) Arrays for Relational Database Operations. Revision. , 1980 .

[21]  Benjamin W. Wah,et al.  The Design of Optimal Systolic Arrays , 1985, IEEE Transactions on Computers.

[22]  E.T.L. Omtzigt,et al.  SYSTARS: A CAD tool for the synthesis and analysis of VLSI systolic/wavefront arrays , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[23]  Zvi M. Kedem,et al.  Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays , 2017, IEEE Trans. Parallel Distributed Syst..

[24]  Dan I. Moldovan,et al.  ADVIS: A Software Package for the Design of Systolic Arrays , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Leslie Lamport,et al.  The parallel execution of DO loops , 1974, CACM.

[26]  Sun-Yuan Kung,et al.  On supercomputing with systolic/wavefront array processors , 1984 .

[27]  I. V. Ramakrishnan,et al.  Modular Matrix Multiplication on a Linear Array , 1984, IEEE Trans. Computers.

[28]  Sun-Yuan Kung On supercomputing with systolic/wavefront array processors , 1984, Proceedings of the IEEE.