Fault Diagnosis in Mixed-Signal Circuits via Neural-Network based classification Algorithms

In this work, we implemented and evaluated several learning paradigms for general classification and diagnostic problems arising in mixed-signal circuit testing. The network models evaluated include Restricted Coulomb Energy (RCE) Neural Network, Learning Vector Quantization (LVQ), Decision Trees (C4.5), and Fuzzy Adaptive Resonance Theory (FuzzyArtmap). A Virtual Test Bench (VTB) was developed to pre-process and extract the fault-test dependency information used as input patterns to the various classifiers from a circuit simulator. Validation techniques, such as N-fold cross-validation and bootstrap methods, are employed for evaluating the robustness of network models. The trained networks are evaluated for their performance using test data on the basis of percent error rates obtained via cross validation and bootstrap techniques, time efficiency, memory size, generalization ability to unseen faults.

[1]  Stephen Grossberg,et al.  Fuzzy ARTMAP: A neural network architecture for incremental supervised learning of analog multidimensional maps , 1992, IEEE Trans. Neural Networks.

[2]  Teuvo Kohonen,et al.  Self-Organizing Maps , 2010 .

[3]  L. S. Milor,et al.  A tutorial introduction to research on analog and mixed-signal circuit testing , 1998 .

[4]  J. David Irwin,et al.  The industrial electronics handbook , 1997 .

[5]  M. J. Hudak.  RCE classifiers: theory and practice , 1992 .

[6]  J. MacQueen.  Some methods for classification and analysis of multivariate observations , 1967 .

[7]  Heekuck Oh,et al.  Neural Networks for Pattern Recognition , 1993, Adv. Comput..

[8]  Stephen Grossberg,et al.  Fuzzy ART: Fast stable learning and categorization of analog patterns by an adaptive resonance system , 1991, Neural Networks.

[9]  D. Teegarden,et al.  Using simulation to improve fault coverage of analog and mixed-signal test program sets , 1997, 1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century.

[10]  S. Upadhyaya,et al.  Fault diagnosis of analog circuits using artificial neural networks as signature analyzers , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[11]  Shambhu Upadhyaya,et al.  Linear circuit fault diagnosis using neuromorphic analyzers , 1997 .

[12]  T. Kohonen,et al.  Appendix 2.4 Stopping Rule 2.3 Fine Tuning Using the Basic Lvq1 or Lvq2.1 Lvq Pak: a Program Package for the Correct Application of Learning Vector Quantization Algorithms , 1992 .

[13]  Muhammad H. Rashid.  SPICE for Circuits and Electronics Using PSPICE , 1990 .

[14]  Li Yan,et al.  On fault diagnosis of analog circuits with tolerance using simulated annealing optimization algorithm , 1992, Proceedings of the 1992 International Conference on Industrial Electronics, Control, Instrumentation, and Automation.

[15]  B. Efron.  The jackknife, the bootstrap, and other resampling plans , 1987 .

[16]  Mohamad T. Musavi,et al.  On the training of radial basis function classifiers , 1992, Neural Networks.

[17]  Celal Batur,et al.  Hopfield/ART-1 Neural Networks based Fault Detection and Isolation , 1992 .

[18]  S. Grossberg,et al.  Fuzzy ART: an adaptive resonance algorithm for rapid, stable classification of analog patterns , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

[19]  Gerald Sommer,et al.  Pattern Recognition by Self-Organizing Neural Networks , 1994 .

[20]  Stephen Grossberg,et al.  A massively parallel architecture for a self-organizing neural pattern recognition machine , 1988, Comput. Vis. Graph. Image Process..

[21]  J.W. Bandler,et al.  Fault diagnosis of analog circuits , 1985, Proceedings of the IEEE.

[22]  Simon Haykin,et al.  Neural Networks: A Comprehensive Foundation , 1998 .

[23]  D. Majernik,et al.  Behavioral fault simulation of large mixed-signal UUTs using the Saber simulator , 1998, 1998 IEEE AUTOTESTCON Proceedings. IEEE Systems Readiness Technology Conference. Test Technology for the 21st Century (Cat. No.98CH36179).