论文信息 - Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]

For original article see H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko and T. Sumi, ibid., vol.31, pp.1157-69 (Aug. 1996). I have read with a great interest the article by H. Suzuki et al. I am familiar with their work, and I found their approach interesting. The idea used to simplify the leading zero anticipator (LZA) I found innovative and an improvement over the one used in the IBM RS/6000. However, I found the LZ counter circuit shown in the paper similar to the LZ counter circuit that I have published previously in the period from 1992-94.

[1] Vojin G. Oklobdzija,et al. An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[2] Vojin G. Oklobdzija. Algorithmic design of a hierarchical and modulator leading zero detector circuit , 1993 .

[3] Vojin G. Oklobdzija,et al. An implementation algorithm and design of a novel leading zero detector circuit , 1992, [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers.