An Approach for PDN Simplification of a Mobile Processor

Todays, the power optimization of a mobile product aims at designing more effective power/ground layout structure without performance degradation. Thus, it is necessary to optimize power/ground domains based on analyzing the performance of composing IPs between adjacent power domains. In this work, a design solution for power optimization based on CPS (chip-package-system) co-analysis was applied at a full chip scale using a mobile processor. A current noise model of merging IPs under operation scenarios was extracted and noise impact by merging the power domain of neighboring IPs was analyzed including package and board electrical properties. By simulation results using the proposed approach, the number of power domains can be reduced up to 32%. In order to verify the suggested approach, the performance of package assembled samples was measured and compared between merged and separate power domains. As a result, the validation of the applied analysis approach was successfully demonstrated by not measuring any performance degradation. In addition, we also applied a machine-learning technique for CPS co-analysis to effectively optimize a system-level PDN design. It was demonstrated to significantly reduce the number of possible combinations in a PDN configuration with a wide-range solution space. Consequently, the proposed design solution for power domain optimization is expected to be effectively applicable for maintaining the competitiveness of product development in various industry applications.