A VHDL Implementation of Low Area Advance Encryption Standard Processor

In this work our aim to achieve a high through put compact. AES S-Box with minimum area consumption. To improve architectures are proposed for implementation of S-Box and Inverse S-box needed in the Advanced Encryption Standard (AES). Unlike previous work which rely on look-up table to implement the Subbytes and Invsubbytes transformations of the AES algorithm the proposed design employs Combinational logic only for implementing Subbytes (S-Box) and InvsubBytes (Inverse SBox). The resulting hardware requirements are presented for proposed design and compared by ROMbased and Pre-Computation technique and improve with this two technique a new technique is Galois field arithmetic. KeywordsAdvanced Encryption Standard, VLSI architectures, Data Encryption, S-Box, Sub-byte Encryption INTRODUCTION The AES algorithm is a symmetric block cipher that processes data blocks of 128 bits using a cipher key of length 128, 192, or 256 bits. Each data block consists of a 4 × 4 array of bytes called the state, on which the basic operations of the AES algorithm are performed. The AES encryption/decryption procedure is shown in Fig. 1. After an initial round key addition, a round function consisting of four different transformations — SubBytes(), ShiftRows(), MixColumns(), and AddRoundKey() — is applied to the data block (i.e., the state array). Corresponding Author* Emailnimmi.gupta877@gmail.com The round function is performed iteratively 10, 12, or 14 times, depending on the key length. Note that in the last round MixColumns() is not applied. The four transformations are described briefly as follows [1]: • SubBytes():a nonlinear byte substitution that operates independently on each byte of the state using a substitution table (the SBox) • ShiftRows():a circular shifting operation on the rows of the state with different numbers of bytes (offsets) • MixColumns(): the operation that mixes the bytes in each column by the [Gupta et al., 3(1): Jan-Mar., 2013] ISSN: 2277-5528 Int. J. of Engg. Sci. & Mgmt. (IJESM), Vol. 3, Issue 1: Jan.-Mar.: 2013,86-90 multiplication of the state with a fixed polynomial modulo x4 + 1. • AddRoundKey(): an XOR operation that adds a round key to the state in each iteration, where the round keys are generated during the key expansion phase smoothly changing the other properties. The major properties of concern as far as a speech signal is concerned are its pitch and envelope information. The decryption procedure of the AES is basically the inverse of each transformation (InvSubBytes(), InvShiftRows(), InvMixColumns(), and AddRoundKey()) in reverse order. However, the order of InvSubBytes() and InvShiftRows() is indifferent. The decryption procedure thus can be rearranged as shown in Fig. 1, where the InvRoundKey is obtained by applying InvMixColumns() to the respective original RoundKey [1]. Such a structural similarity in both the encryption and decryption procedures makes hardware implementation easier. The SubBytes() transformation (S-Box operation), which consists of amultiplicative inverse over GF(28) and an affine transform, is the most critical part of the AES algorithm in terms of computational complexity. However, the S-Box operation is required for both encryption and key expansion. Conventionally, the coefficients of the S-Box and inverse S-Box are stored in the LUTs, or a hard-wired multiplicative inverter over GF(28) can be used, together with an affine transform circuit. A dedicated inverter, however, has a high area overhead. We propose an efficient implementation by a transformation of the S-Box over the finite field. METHODOLOGY Composite Field Arithmetic The non-LUT-based implementations of the AES algorithm are able to exploit the advantage of subpipelining further. Nevertheless, these approaches may have high hardware complexities. Although two Galois Fields of the same order are isomorphic, the complexity of the field operations may heavily depend on the representations of the field elements. Composite field arithmetic can be employed to reduce the hardware complexity. We call two pairs and a composite field [12] if • GF(2) is constructed from by GF(2)