Functional verification methodology of a 32-bit RISC microprocessor

With the increasing complexity of Microprocessor, the verification of the design becomes more and more important. This paper presented a simulation-based functional verification methodology to validate a 32-bit RISC microprocessor (named as FDU32). In the paper, pseudo-random generating and pipeline-focus generating are used as the main method to generate testbenches. Besides, the whole verification environment is set up to improve the automation and efficiency of the process. In addition, code coverage analysis is used to guarantee the quality of the verification.

[1]  Carl Ramey,et al.  Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[2]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[3]  Janick Bergeron,et al.  Writing Testbenches: Functional Verification of HDL Models , 2000 .

[4]  Fumiyasu Hirose,et al.  Automatic program generator for simulation-based processor verification , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[5]  Fumiyasu Hirose,et al.  Behavioral design and test assistance for pipelined processors , 1992, Proceedings First Asian Test Symposium (ATS `92).

[6]  Randal E. Bryant,et al.  Formal verification of an ARM processor , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).