Parameterized Path Based Randomized Oblivious Minimal Path Routing with Fault Tolerance in 2D Mesh Network on Chip

Fault tolerance has become one of the major concerns in routers or links as the transistor feature size is shrinking leading to gate scaling in Network on Chip (NoC). More number of processing elements (PE) are being incorporated for interconnection in system on chip, making it difficult to deliver packets to the destination. Overcome from permanent fault can be achieved using efficient routing algorithms whereas retransmission of faulty packet resolve transient faults in the network. Routing would be efficient, if it can handle multiple faults in the path while managing congestion in the network. In this paper a path based randomized oblivious minimal routing algorithm (FTPROM) with fault tolerance is proposed. FTPROM is derived from parameterized PROM is an oblivious routing. It uses probability functions to provide more diversity to route in the network and handles congestion in better way. Routing follows minimal path in presence of faults both as node and link failure. Simulation results show that the proposed algorithm is effective in terms of congestion handling, latency, and degree of adaptiveness.

[1]  Jie Wu,et al.  A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model , 2003, IEEE Trans. Computers.

[2]  Pasi Liljeberg,et al.  Fault tolerant distributed routing algorithms for mesh Networks-on-Chip , 2009, 2009 International Symposium on Signals, Circuits and Systems.

[3]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[4]  Vijay Laxmi,et al.  Minimal Path, Fault Tolerant, QoS Aware Routing with Node and Link Failure in 2-D Mesh NoC , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

[5]  Radu Marculescu,et al.  Towards on-chip fault-tolerant communication , 2003, ASP-DAC '03.

[6]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1998, ISCA '98.

[7]  Alain Greiner,et al.  A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[8]  José Duato A Theory of Fault-Tolerant Routing in Wormhole Networks , 1997, IEEE Trans. Parallel Distributed Syst..

[9]  Mahmut T. Kandemir,et al.  Fault tolerant algorithms for network-on-chip interconnect , 2004, IEEE Computer Society Annual Symposium on VLSI.

[10]  Srinivas Devadas,et al.  Path-based, Randomized, Oblivious, Minimal routing , 2009, 2009 2nd International Workshop on Network on Chip Architectures.