A parallel HEVC encoder scheme based on Multi-core platform

In this paper, we propose a parallel HEVC encoder scheme based on multi-core platform, which provides maximized parallel scalability by exploiting two-level parallelism, namely, the frame level parallelism and the CTB level parallelism. Inspired by the intra-CTB row level parallelism of WPP in HEVC, we investigate the inter-frame CTB prediction dependency to its reference CTBs, and find the inter-CTB correlation. Using this inter-correlation, we divide a frame into CTB units and create CTB-row level coding threads when their corresponding reference CTBs are available. Each thread is bonded to a processing core, therefore, both intra- and inter-CTB rows can be encoded in parallel. Moreover, we introduce a priority scheduling mechanism to control the coding threads. Experiments on Tilera-Gx36 multi-core platform show that, compared with serial execution, the proposed method achieves 3.6 and 4.3 times speedup for 1080P and 720P video sequences, respectively.