Decomposition of Boolean Functions Specified by Cubes

We study the problem of decomposing a Boolean function into a set of functions with fewer arguments. This problem has considerable practical importance in VLSI, for example, for designs using field-programmable gate arrays. The decomposition problem is old, and well understood when the function to be decomposed is specified by a truth table, or has one output only. However, modern design tools handle functions with many outputs and represent them by cubes, for reasons of efficiency. We develop a comprehensive theory of serial decompositions for multiple-output, partially specified, Boolean functions represented by cubes. A function f (x1 , . . . , xn) has a serial decomposition if it can be expressed as h(u1 , . . . , ur, g(v1 , . . . , vs)), where U = {u1 , . . . , ur} and V = {v1 , . . . , vs} are subsets of the set X = {x1 , . . . , xn} of input variables, and g and h have fewer input variables than f. The theory uses generalized set systems (which, in turn, are generalized partitions), which we call blankets.

[1]  Henry Selvaraj,et al.  Balanced multilevel decomposition and its applications in FPGA-based synthesis , 1995 .

[2]  Tadeusz Luba,et al.  A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis , 1995, VLSI Design.

[3]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[4]  Massoud Pedram,et al.  OBDD-based function decomposition: algorithms and implementation , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  M. Shams.  Asynchronous Circuits , 2005 .

[6]  Shih-Chieh Chang,et al.  Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Sarma Vrudhula,et al.  EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Sze-Tsen Hu.  ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .

[9]  Tadeusz Łuba,et al.  Multi-level logic synthesis based on decomposition , 1994 .

[10]  Tiziano Villa,et al.  Satisfaction of input and output encoding constraints , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Richard M. Karp,et al.  Minimization Over Boolean Graphs , 1962, IBM J. Res. Dev..

[12]  Tadeusz Luba.  Multi-level logic synthesis based on decomposition , 1994, Microprocess. Microsystems.

[13]  Pierre Marchal,et al.  Field-programmable gate arrays , 1999, CACM.

[14]  Jonathan Rose,et al.  Synthesis methods for field programmable gate arrays , 1993 .

[15]  Janusz A. Brzozowski,et al.  Blanket Algebra For Multiple-Valued Function Decomposition , 1997 .

[16]  Wei Wan,et al.  A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[17]  Rajeev Murgai,et al.  Improved logic synthesis algorithms for table look up architectures , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[18]  Lech Józwiak,et al.  Information relationships and measures in application to logic design , 1999, Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329).

[19]  Wen-Zen Shen,et al.  Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping , 1995, 32nd Design Automation Conference.

[20]  H. A. Curtis,et al.  A new approach to The design of switching circuits , 1962 .

[21]  Mpj Mario Stevens,et al.  Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis , 1995 .

[22]  Carl Sechen,et al.  A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis , 1995, 32nd Design Automation Conference.

[23]  J. Hartmanis,et al.  Algebraic Structure Theory Of Sequential Machines , 1966 .

[24]  Seiyang Yang,et al.  PLADE: a two-stage PLA decomposition , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Lech Jóźwiak,et al.  General Decomposition and Its Use in Digital Circuit Synthesis , 1995 .