Coverage Driven Test Generation Framework for RTL Functional Verification

Functional verification is widely recognized as the bottleneck of the hardware design cycle. The coverage-driven verification approach makes coverage the core engine that drives the whole verification flow, which enables reaching high quality verification in a timely manner. In this paper, we present a coverage driven test generation methodology and a set of tools. We present a novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving. We present a novel approach to generate functional vectors based on assertions for RTL design verification. Our approach combines program-slicing based design extraction, word-level SAT and dynamic searching techniques. We also present a coverage analysis method based on VCD file, which only replaying the simulation of the control statements in the HDL description. Experimental results show the efficiency of our methodology.

[1]  Yang Guo,et al.  Automatic circuit extractor for HDL description using program slicing , 2004, Journal of Computer Science and Technology.

[2]  Avi Ziv,et al.  Coverage directed test generation for functional verification using Bayesian networks , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[3]  Wolfgang Roesner,et al.  Comprehensive Functional Verification: The Complete Industry Cycle , 2005 .

[4]  Fabrizio Ferrandi,et al.  An application of genetic algorithms and BDDs to functional testing , 2000, Proceedings 2000 International Conference on Computer Design.

[5]  Sofiène Tahar,et al.  Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

[6]  Kwang-Ting Cheng,et al.  Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques , 2000, DAC.

[7]  K. Keutzer,et al.  Functional Vector Generation for HDL Models Using , 2001 .

[8]  Zhihong Zeng,et al.  Functional Test Generation using Constraint Logic Programming , 2001, VLSI-SOC.

[9]  David G. Chinnery,et al.  A functional validation technique: biased-random simulation guided by observability-based coverage , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[10]  Kurt Keutzer,et al.  Coverage Metrics for Functional Validation of Hardware Designs , 2001, IEEE Des. Test Comput..

[11]  Sofiène Tahar,et al.  Design and verification of SystemC transaction-level models , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Masahiro Fujita,et al.  Automatic test pattern generation for functional RTL circuits using assignment decision diagrams , 2000, Proceedings 37th Design Automation Conference.