The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm

This paper describes an analytical modeling tool called Bitlet that can be used, in a parameterized fashion, to understand the affinity of workloads to processing-in-memory (PIM) as opposed to traditional computing. The tool uncovers interesting trade-offs between operation complexity (cycles required to perform an operation through PIM) and other key parameters, such as system memory bandwidth, data transfer size, the extent of data alignment, and effective memory capacity involved in PIM computations. Despite its simplicity, the model has already proven useful. In the future, we intend to extend and refine Bitlet to further increase its utility.

[1]  Karthikeyan Sankaralingam,et al.  Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.

[2]  Gregory S. Snider,et al.  ‘Memristive’ switches enable ‘stateful’ logic operations via material implication , 2010, Nature.

[3]  William J. Dally,et al.  Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems , 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[4]  Nagarajan Raghavan,et al.  Recommended Methods to Study Resistive Switching Devices , 2018, Advanced Electronic Materials.

[5]  Mark D. Hill,et al.  Gables: A Roofline Model for Mobile SoCs , 2019, 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[6]  Scott A. Mahlke,et al.  In-Memory Data Parallel Processor , 2018, ASPLOS.

[7]  John L. Gustafson,et al.  Reevaluating Amdahl's law , 1988, CACM.

[8]  U. Böttger,et al.  Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations , 2012, Nanotechnology.

[9]  Anupam Chattopadhyay,et al.  ReVAMP: ReRAM based VLIW architecture for in-memory computing , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[10]  Uri C. Weiser,et al.  MAGIC—Memristor-Aided Logic , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Mark D. Hill,et al.  Amdahl's Law in the Multicore Era , 2008 .

[12]  Yang Liu,et al.  Willow: A User-Programmable SSD , 2014, OSDI.

[13]  Shimeng Yu,et al.  Metal–Oxide RRAM , 2012, Proceedings of the IEEE.

[14]  Shih-Hung Chen,et al.  Phase-change random access memory: A scalable technology , 2008, IBM J. Res. Dev..