Ultralow-power technology

An ultralow-standby-power technology has been developed in both 0.18-� m and 0.13-� m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 � m 2 and 2.34 � m 2 , corresponding respectively to the 0.18-� m and 0.13-� m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25C and is less than 400 fA per cell at 1.5 V, 85C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

[1]  T. Chao,et al.  A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs , 1999 .

[2]  A. Lauwers,et al.  Silicide and Shallow Trench Isolation line width dependent stress induced junction leakage , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[3]  C. Hu,et al.  Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling , 2001 .

[4]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[5]  D. Wen,et al.  Tunneling leakage in Ge preamorphized shallow junctions , 1988 .

[6]  Ding-Ming Kwai,et al.  Detection of SRAM cell stability by lowering array supply voltage , 2000, Proceedings of the Ninth Asian Test Symposium.

[7]  R. Mahnkopf,et al.  A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[8]  K. Takeuchi.  Channel size dependence of dopant-induced threshold voltage fluctuation [deep submicron MOSFETs] , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[9]  Dae-Hee Weon,et al.  Roles of sidewall oxidation in the devices with shallow trench isolation , 1999 .

[10]  Daniel C. Cole,et al.  Optimization criteria for SRAM design: lithography contribution , 1999, Advanced Lithography.

[11]  S. Saini,et al.  Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m MOSFET's with epitaxial and /spl delta/-doped channels , 1999 .

[12]  C. Hu,et al.  Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model , 1992 .

[13]  Jae-Beom Park,et al.  A shallow trench isolation using nitric oxide (NO)-annealed wall oxide to suppress inverse narrow width effect , 2000 .

[14]  A. Ono,et al.  TED control technology for suppression of reverse narrow channel effect in 0.1 /spl mu/m MOS devices , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[15]  Ajit K. Srivastava,et al.  Design and integration considerations for end-of-the roadmap ultrashallow junctions , 2000 .

[16]  Soon Moon June,et al.  High density low power full CMOS SRAM cell technology with STI and CVD Ti/TiN barrier metal , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[17]  Mankoo Lee,et al.  Static noise margin and soft-error rate simulations for thin film transistor cell stability in a 4 Mbit SRAM design , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[18]  The leakage current improvement in an ultrashallow junction NMOS with Co silicided source and drain , 2000 .

[19]  I. Chen,et al.  A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

[20]  T. Chan,et al.  Subbreakdown drain leakage current in MOSFET , 1987, IEEE Electron Device Letters.

[21]  F. S. Shoucair,et al.  Scaling, subthreshold, and leakage current matching characteristics in high-temperature (25 degrees C-250 degrees C) VLSI CMOS devices , 1989 .