Nonscaling of MOSFET's linear resistance in the deep submicrometer regime

This paper investigates the scaling properties of deep submicron MOSFET's and shows that, while in a wide range of channel lengths they can be represented as composed by a scaling intrinsic and a nonscaling parasitic part, this picture does no longer hold for shorter transistors. A nonscaling of the total resistance R/sub TOT/=[V/sub DS//I/sub DS/] of short devices is observed, and its impact on parasitic resistances and effective channel length extraction is discussed. A possible explanation is suggested in relation to the two-dimensional substrate doping redistribution linked to reverse-short-channel effects.

[1]  D. F. Nelson,et al.  High‐field drift velocity of electrons at the Si–SiO2 interface as determined by a time‐of‐flight technique , 1983 .

[2]  J. A. López-Villanueva,et al.  Universality of electron mobility curves in MOSFETs: a Monte Carlo study , 1995 .

[3]  Yuan Taur,et al.  On "effective channel length" in 0.1-μm MOSFETs , 1995, IEEE Electron Device Letters.

[4]  An etive Channel Length Determination od for LDD MOSFET's , 1996 .

[5]  C. Fiegna,et al.  Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions , 1993, Proceedings of IEEE International Electron Devices Meeting.

[6]  Y. Taur,et al.  A new 'shift and ratio' method for MOSFET channel-length extraction , 1992, IEEE Electron Device Letters.

[7]  G.J. Hu,et al.  Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's , 1987, IEEE Transactions on Electron Devices.

[8]  H. Iwai,et al.  A 40 nm gate length n-MOSFET , 1995 .

[9]  J.Y.-C. Sun,et al.  On the accuracy of channel length characterization of LDD MOSFET's , 1986, IEEE Transactions on Electron Devices.

[10]  C. Mazure,et al.  Guidelines for reverse short-channel behavior , 1989, IEEE Electron Device Letters.

[11]  M. R. Pinto,et al.  Explanation of reverse short channel effect by defect gradients , 1993, Proceedings of IEEE International Electron Devices Meeting.

[12]  Hiroshi Iwai,et al.  Fabrication of sub‐50‐nm gate length n‐metal–oxide–semiconductor field effect transistors and their electrical characteristics , 1995 .

[13]  A.T. Wu,et al.  Deep-submicrometer MOS device fabrication using a photoresist-ashing technique , 1988, IEEE Electron Device Letters.