Design of Improved Arithmetic Logic Unit in Quantum-Dot Cellular Automata

The quantum-dot cellular automata (QCA) can be replaced to overcome the limitation of CMOS technology. An arithmetic logic unit (ALU) is a basic structure of any computer devices. In this paper, design of improved single-bit arithmetic logic unit in quantum dot cellular automata is presented. The proposed structure for ALU has AND, OR, XOR and ADD operations. A unique 2:1 multiplexer, an ultra-efficient two-input XOR and a low complexity full adder are used in the proposed structure. Also, an extended design of this structure is provided for two-bit ALU in this paper. The proposed structure of ALU is simulated by QCADesigner and simulation result is evaluated. Evaluation results show that the proposed design has best performance in terms of area, complexity and delay compared to the previous designs.

[1]  Ahmad Habibizad Navin,et al.  Content addressable memory cell in quantum-dot cellular automata , 2016 .

[2]  Saeed Rasouli Heikalabad,et al.  A novel multiplexer-based structure for random access memory cell in quantum-dot cellular automata , 2017 .

[3]  R. Pandey Design and Implementation of 16-bit Arithmetic Logic Unit using Quantum dot Cellular Automata (QCA) Technique , 2014 .

[4]  Mohammad Mohammadi,et al.  An efficient design of full adder in quantum-dot cellular automata (QCA) technology , 2016, Microelectron. J..

[5]  Saeed Rasouli Heikalabad,et al.  Binary to gray and gray to binary converter in quantum-dot cellular automata , 2017 .

[6]  Shaahin Angizi,et al.  Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells , 2016, J. Comput. Sci..

[7]  T.J. Dysart,et al.  > Replace This Line with Your Paper Identification Number (double-click Here to Edit) < 1 , 2001 .

[8]  Nima Jafari Navimipour,et al.  A new three-level fault tolerance arithmetic and logic unit based on quantum dot cellular automata , 2018 .

[9]  P. Douglas Tougaw,et al.  An Alternative Geometry for Quantum Cellular Automata , 1998, VLSI Design.

[10]  Bibhash Sen,et al.  Design of Testable Adder in Quantum-dot Cellular Automata with Fault Secure Logic , 2017, Microelectron. J..

[11]  Debasis Mitra,et al.  Design of a practical fault-tolerant adder in QCA , 2016, Microelectron. J..

[12]  P. D. Tougaw,et al.  Logical devices implemented using quantum cellular automata , 1994 .

[13]  Bibhash Sen,et al.  Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU , 2014, ACM J. Emerg. Technol. Comput. Syst..

[14]  Keivan Navi,et al.  Towards ultra-efficient QCA reversible circuits , 2017, Microprocess. Microsystems.

[15]  Saeed Rasouli Heikalabad,et al.  A novel fault tolerant majority gate in quantum-dot cellular automata to create a revolution in design of fault tolerant nanostructures, with physical verification , 2018 .

[16]  Saeed Rasouli Heikalabad,et al.  A unique structure for the multiplexer in quantum-dot cellular automata to create a revolution in design of nanostructures , 2017 .

[17]  P. K. Dakhole,et al.  Design and implementation of 4-bit arithmetic logic unit using Quantum Dot Cellular Automata , 2013, 2013 3rd IEEE International Advance Computing Conference (IACC).

[18]  Earl E. Swartzlander,et al.  A First Step Toward Cost Functions for Quantum-Dot Cellular Automata Designs , 2014, IEEE Transactions on Nanotechnology.

[19]  Ahmad Habibizad Navin,et al.  Midpoint Memory: A Special Memory Structure for Data-Oriented Models Implementation , 2015, J. Circuits Syst. Comput..

[20]  Saeed Rasouli Heikalabad,et al.  A testable parity conservative gate in quantum-dot cellular automata , 2017 .

[21]  Saeed Rasouli Heikalabad,et al.  A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis , 2018, The Journal of Supercomputing.

[22]  E. N. Ganesh Implementation and simulation of arithmetic logic unit, shifter and Multiplier in Quantum cellular automata technology. , 2010 .

[23]  Saeed Rasouli Heikalabad,et al.  Reversible Flip-Flops in Quantum-Dot Cellular Automata , 2017, International Journal of Theoretical Physics.

[24]  Saeed Rasouli Heikalabad,et al.  A Three-Layer Full Adder/Subtractor Structure in Quantum-Dot Cellular Automata , 2017 .

[25]  M. M. Abutaleb Robust and efficient quantum-dot cellular automata synchronous counters , 2017, Microelectron. J..

[26]  Michael A. Wilson,et al.  Nanotechnology: Basic Science and Emerging Technologies , 2002 .

[27]  Saeed Rasouli Heikalabad,et al.  A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis , 2018 .

[28]  Ramesh Karri,et al.  Quantum-Dot Cellular Automata Design Guideline , 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[29]  P. Gargini,et al.  The International Technology Roadmap for Semiconductors (ITRS): "Past, present and future" , 2000, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuits Symposium. 22nd Annual Technical Digest 2000. (Cat. No.00CH37084).

[30]  Bibhash Sen,et al.  On the reliability of majority logic structure in quantum-dot cellular automata , 2016, Microelectron. J..

[31]  Milad Sangsefidi,et al.  Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover , 2015, IEEE Transactions on Nanotechnology.

[32]  Bibhash Sen,et al.  Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCA , 2012, 2012 International Symposium on Electronic System Design (ISED).

[33]  Ronald F. DeMara,et al.  Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder , 2015, Microelectron. J..