The dynamic threshold MOS transistor (DTMOS) built on an SOI substrate is one candidate to realize low-power one-chip RF and high-speed digital integrated circuits for wireless communication systems and optical fiber links. Scaling down the characteristic length of the DTMOS is aggressively performed, and the cut-off frequency (f/sub T/) has been drastically increased. Although the f/sub T/ is steeply rising every year, improvement of the maximum oscillation frequency (f/sub max/) is very slow. This is due to a limitation of the silicide based gate resistance (Rg) in the conventional logic CMOS process. Many interesting ways with optimized layout such as folded gate finger and multi-finger pattern have been proposed, and great efforts to make Rg small have been made. The most effective way to perform further reduction of Rg is to use a low resistive metal-gate or a metallic overlay-gate that is fabricated on the poly-Si fine gate. In this paper, we propose an 80 nm gate SOI-nDTMOS with a new gate structure. The key is to introduce a metallic overlay-gate process into the conventional logic CMOS fabrication process. Using the metallic overlay-gate structure, we achieved the f/sub max/ of 185 GHz at low bias voltage, which is, in our knowledge, the world record ever reported for Si MOSFETs.