Linear Systolic Arrays for Matrix Comutations

Abstract The paper presents a systematic method to derive linear processor arrays from given two-dimensional arrays. The proposed hierarchical approach leads to one-dimensional computational arrays for an important class of algorithms which need O(n3) computational steps in a sequential implementation. The proposed linear arrays share the following properties: matching of the computation rate and available I/O bandwidth, lexicographical order of input/output data, modularity, O(n) computational cells, O(n2) delay elements, fault tolerance, and the use of pipelined arithmetic units. As an example a linear array for matrix inversion is given.

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