Defect Reduction Paths in SiC Epitaxy

This paper discusses formation mechanisms and potential paths to reduce defect density in current SiC epitaxy technology. Comprehensive optimization efforts have resulted in defect density measured by laser light scattering below 0.5 cm-2 for 30 um thick epi wafers. Possible approaches to reduce basal plane dislocations and mitigate interfacial dislocations are discussed. The progress in epitaxy defect reduction has been made on the foundation of the high quality 100mm substrates. The average and median BPD density is 700 cm-2 and 500 cm-2, respectively, and a low TSD density is also achieved simultaneously with both average and median values around 350 cm-2. High quality and low stress 150mm substrates have been obtained with very low TSD density of <150 cm-2.

[1]  Jie Zhang,et al.  Progress in Large-Area 4H-SiC Epitaxial Layer Growth in a Warm-Wall Planetary Reactor , 2014 .

[2]  Jie Zhang,et al.  Progress in Growth of Thick Epitaxial Layers on 4 Degree Off-Axis 4H SiC Substrates , 2012 .

[3]  M. O'loughlin,et al.  Correlation of Extended Defects on Carrier Lifetime in Thick SiC Epilayers , 2012 .

[4]  T. Kimoto,et al.  Doping-Induced Lattice Mismatch and Misorientation in 4H-SiC Crystals , 2012 .

[5]  H. Tsuchida,et al.  Correlation between Thermal Stress and Formation of Interfacial Dislocations during 4H-SiC Epitaxy and Thermal Annealing , 2011 .

[6]  K. Hobart,et al.  Structure and Morphology of Inclusions in 4° Offcut 4H-SiC Epitaxial Layers , 2011 .

[7]  A. Agarwal,et al.  Influence of Shockley Stacking Fault Generation on Electrical Behavior of 4H-SiC 10 kV MPS Diodes , 2010 .

[8]  J. Sumakeris,et al.  Morphology of basal plane dislocations in 4H-SiC homoepitaxial layers grown by chemical vapor deposition , 2007 .

[9]  K. Kojima,et al.  Influence of growth conditions on basal plane dislocation in 4H-SiC epitaxial layer , 2004 .

[10]  H. Lendenmann,et al.  Properties and origins of different stacking faults that cause degradation in SiC PiN diodes , 2004 .

[11]  Marek Skowronski,et al.  Dislocation conversion in 4H silicon carbide epitaxy , 2002 .

[12]  H. Lendenmann,et al.  Long Term Operation of 4.5kV PiN and 2.5kV JBS Diodes , 2001 .

[13]  H. Tsuchida,et al.  Influence of Growth Conditions and Substrate Properties on Formation of Interfacial Dislocations and Dislocation Half-loop Arrays in 4H-SiC(0001) and (000-1) Epitaxy , 2008 .