RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs
暂无分享,去创建一个
In Man Kang | Byung-Gook Park | Seongjae Cho | Byung-Gook Park | Seongjae Cho | I. Kang | K. Kim | Kyung Rok Kim
[1] Donhee Ham,et al. Nanotechnology: High-speed integrated nanowire circuits , 2005, Nature.
[2] Tsu-Jae King,et al. A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain , 2005, IEEE Transactions on Electron Devices.
[3] I. Chung,et al. NANOCAD Framework for Simulation of Quantum Effects in Nanoscale MOSFET Devices , 2006 .
[4] Wei Lu,et al. TOPICAL REVIEW: Semiconductor nanowires , 2006 .
[5] Mark S. Lundstrom,et al. A computational study of thin-body, double-gate, Schottky barrier MOSFETs , 2002 .
[6] Lianmao Peng,et al. Current-voltage characteristics and parameter retrieval of semiconducting nanowires , 2006 .
[7] Chih-Hong Hwang,et al. The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit , 2009 .
[8] Yun Seop Yu,et al. A SPICE-Compatible New Silicon Nanowire Field-Effect Transistors (SNWFETs) Model , 2009, IEEE Transactions on Nanotechnology.
[9] Charles M Lieber,et al. Semiconductor nanowires , 2006 .
[10] Sorin Cristoloveanu,et al. Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .
[11] Yiming Li,et al. DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit , 2009 .
[12] J. Fischer,et al. Synthesis and postgrowth doping of silicon nanowires , 2005 .
[13] Y. Tsividis. Operation and modeling of the MOS transistor , 1987 .
[14] B. Iñíguez,et al. Continuous analytic I-V model for surrounding-gate MOSFETs , 2004, IEEE Electron Device Letters.
[15] Charles M. Lieber,et al. High Performance Silicon Nanowire Field Effect Transistors , 2003 .
[16] Ru Huang,et al. Investigation of Parasitic Effects and Design Optimization in Silicon Nanowire MOSFETs for RF Applications , 2008, IEEE Transactions on Electron Devices.
[17] Byung-Gook Park,et al. Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process , 2010 .
[18] Jong-Ho Lee,et al. Formation of Ge nanocrystals in a silicon dioxide layer using pulsed plasma-immersion ion implantation , 2009 .
[19] B. Ryu,et al. Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires , 2006, 2006 International Electron Devices Meeting.
[20] Accurate simulation on band-to-band tunneling induced leakage current using a global non-local model , 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.
[21] G. A. Armstrong,et al. Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications , 2007, IEEE Electron Device Letters.
[22] Hyungcheol Shin,et al. Accurate four-terminal RF MOSFET model accounting for the short-channel effect in the source-to-drain capacitance , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..
[23] Chi-Woo Lee,et al. Junctionless multigate field-effect transistor , 2009 .
[24] Ru Huang,et al. Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation , 2007, IEEE Transactions on Electron Devices.
[25] Chi-Woo Lee,et al. Low subthreshold slope in junctionless multigate transistors , 2010 .
[26] Xing Zhang,et al. A Compact Model of Silicon-Based Nanowire MOSFETs for Circuit Simulation and Design , 2008, IEEE Transactions on Electron Devices.
[27] Jean-Pierre Colinge,et al. Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs , 1990 .
[28] Chi-Woo Lee,et al. Reduced electric field in junctionless transistors , 2010 .
[29] G. S. Samudra,et al. A new robust non-local algorithm for band-to-band tunneling simulation and its application to Tunnel-FET , 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.
[30] A. Bindal,et al. Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits , 2008, IEEE Transactions on Nanotechnology.
[31] F. Balestra,et al. Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.
[32] Chi-Woo Lee,et al. High-Temperature Performance of Silicon Junctionless MOSFETs , 2010, IEEE Transactions on Electron Devices.
[33] Yuan Taur,et al. A Review on Compact Modeling of Multiple-Gate MOSFETs , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[34] N. Collaert,et al. Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.
[35] S. Cristoloveanu,et al. Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices , 2008, IEEE Transactions on Nuclear Science.
[36] K. Endo,et al. Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs , 2007, IEEE Electron Device Letters.
[37] A. Mercha,et al. Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective , 2006, IEEE Transactions on Electron Devices.