On the Steiner tree problem in L/sub 3/-metric [VLSI wiring]

We consider Steiner minimal trees (SMT) in metrics defined by given orientations. The problem is motivated by wiring consideration of VLSI chips when the wiring direction is not restricted to only horizontal and vertical. In particular, we concentrate on the case when the given orientations form angles of 0/spl deg/, 60/spl deg/ and 120/spl deg/ (/spl lambda//sub 3/-metric) since many interesting results can be obtained, which may shed light on other metrics in the family. Specifically, we show that any SMT can be transformed to one with their Steiner points located on the grid points of a multilevel grid, where the number of levels is at most [n-2/2], n being the number of input points. Based on this result, we have developed a Simulated Annealing (SA) based algorithm to generate near-optimal SMT's. Empirical results compared with Euclidean cases are also given.

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