SoC integration challenges for a power management/analog baseband IC for 3G wireless chipsets

An integrated power management/analog baseband integrated circuit has been developed in 0.35 /spl mu/m CMOS technology. The IC features multiple low-dropout (LDO) linear voltage regulators, power switches, DC/DC switching converters, a voice band CODEC, and WCDMA and GSM baseband converters all sharing the same substrate. This paper examines the design challenges associated with power management and analog baseband system on a chip (SoC) integration. Optimal floorplanning, power device isolation, shielding, power distribution, reference generation, and noise reduction strategies and techniques are discussed.

[1]  Hae-Seung Lee,et al.  Study of substrate noise and techniques for minimization , 2004, IEEE Journal of Solid-State Circuits.

[2]  Shoichi Masui,et al.  Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits , 1993 .

[3]  M. Brkovic,et al.  Synchronous rectifiers vs. Schottky diodes in a buck topology for low voltage applications , 1997, PESC97. Record 28th Annual IEEE Power Electronics Specialists Conference. Formerly Power Conditioning Specialists Conference 1970-71. Power Processing and Electronic Specialists Conference 1972.

[4]  P. Welch,et al.  Comprehensive study of substrate noise isolation for mixed-signal circuits , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[5]  Tung-Sheng Chen,et al.  An efficient noise isolation technique for SOC application , 2004 .