Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip
暂无分享,去创建一个
A. Kumar | U.G. Nawathe | M. Hassan | K.C. Yen | A. Ramachandran | D. Greenhill | Ashok Kumar V | D. Greenhill | Umesh Nawathe | Mahmudul Hassan | King C. Yen | Aparna Ramachandran
[1] Hee-Tae Ahn,et al. A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications , 2000, IEEE Journal of Solid-State Circuits.
[2] A. Hafez,et al. Phase mismatch in phase switching frequency dividers , 2003, Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442).
[3] Bingxue Shi,et al. 2/3 divider cell using phase switching technique , 2001 .
[4] J. Hart,et al. Implementation of a 4/sup th/-generation 1.8GHz dual-core SPARC V9 microprocessor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[5] Ajay Bhatia,et al. A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-Chip , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[6] Dennis Chen,et al. Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor , 2006, IEEE Journal of Solid-State Circuits.
[7] Ashok Kumar,et al. An 8-Core 64-Thread 64b Power-Efficient SPARC SoC , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[8] Greg Grohoski. Niagara-2: A highly threaded server-on-a-chip , 2006, 2006 IEEE Hot Chips 18 Symposium (HCS).