Context aware slope based transistor-level aging model

Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in IC design for advanced process technology nodes. This paper proposes a device-level aging assessment and prediction model using the signal slope as aging quantifier, that accounts not only for the intrinsic self-degradation but also for the influence of the surrounding circuit topology. Experimental results indicate the validity of slope as aging quantifier and that aging is underestimated when topology influence is disregarded.

[1]  Ulf Schlichtmann,et al.  Efficiently analyzing the impact of aging effects on large integrated circuits , 2012, Microelectron. Reliab..

[2]  Bo Yang,et al.  Statistical prediction of circuit aging under process variations , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[3]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[4]  Ulf Schlichtmann,et al.  Aging analysis of circuit timing considering NBTI and HCI , 2009, 2009 15th IEEE International On-Line Testing Symposium.

[5]  Yu Wang,et al.  NBTI-aware statistical circuit delay assessment , 2009, 2009 10th International Symposium on Quality Electronic Design.

[6]  Yu Cao,et al.  Statistical prediction of NBTI-induced circuit aging , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[7]  Ku He,et al.  Temperature-aware NBTI modeling and the impact of input vector control on performance degradation , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[8]  Yu Wang,et al.  Circuit-level delay modeling considering both TDDB and NBTI , 2011, 2011 12th International Symposium on Quality Electronic Design.

[9]  Jordi Suñé,et al.  Reliability Wearout Mechanisms in Advanced CMOS Technologies , 2009 .

[10]  Takayasu Sakurai,et al.  Delay analysis of series-connected MOSFET circuits , 1991 .

[11]  Gaetano Palumbo,et al.  An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Sangwoo Han,et al.  NBTI-aware statistical timing analysis framework , 2010, 23rd IEEE International SOC Conference.

[13]  Fan Yang,et al.  Statistical reliability analysis under process variation and aging effects , 2009, 2009 46th ACM/IEEE Design Automation Conference.