Stability analysis of a 400 mV 4-transistor CMOS-SOI SRAM cell operated in subthreshold

This paper addresses the design robustness of CMOS SOI memory cells operating at Ultra-Low-Voltage, ULV. An analytical approach to the stability problem of SRAM cells is presented. The analysis is performed for a 6-transistor and 4-transistor CMOS SOI memory cell based on an analytical subthreshold estimation model.

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