Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality
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Kees G. W. Goossens | Erik Jan Marinissen | Jos Huisken | Joe Swenton | Santosh Malagi | Zhan Gao | Min-Chun Hu
[1] Edward J. McCluskey,et al. Gate exhaustive testing , 2005, IEEE International Conference on Test, 2005..
[2] Friedrich Hapke,et al. Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates , 2012, 2012 17th IEEE European Test Symposium (ETS).
[3] Fan Yang,et al. Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests , 2014, 2014 IEEE 23rd Asian Test Symposium.
[4] Friedrich Hapke,et al. Cell-Aware Test , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Friedrich Hapke,et al. Cell-aware analysis for small-delay effects and production test results from different fault models , 2011, 2011 IEEE International Test Conference.
[6] Achim Graupner,et al. A comprehensive workflow and methodology for parasitic extraction , 2012 .
[7] Mathias Beike,et al. Digital Integrated Circuits A Design Perspective , 2016 .
[8] Cheng-Wen Wu,et al. Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).
[9] Antonio Rubio,et al. A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[10] E. Augendre,et al. Experimental verification of SRAM cell functionality after hard and soft gate oxide breakdowns , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..
[11] Camelia Hora,et al. Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality , 2008, 2008 IEEE International Test Conference.
[12] Camelia Hora,et al. Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs , 2009, 2009 International Test Conference.
[13] Bernd Becker,et al. Automatic Test Pattern Generation for Interconnect Open Defects , 2008, 26th IEEE VLSI Test Symposium (vts 2008).
[14] Kees G. W. Goossens,et al. Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library , 2019, 2019 IEEE International Test Conference (ITC).
[15] Daniel Arumí,et al. Experimental Characterization of CMOS Interconnect Open Defects , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Vishwani D. Agrawal,et al. Tutorial: Delay Fault Models and Coverage , 1998 .
[17] Friedrich Hapke,et al. Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects , 2007, 2007 IEEE International Test Conference.
[18] Richard D. Eldred. Test Routines Based on Symbolic Logical Statements , 1959, JACM.
[19] Ayush Singhal,et al. DFM-aware fault model and ATPG for intra-cell and inter-cell defects , 2017, 2017 IEEE International Test Conference (ITC).
[20] Friedrich Hapke,et al. Gate-Exhaustive and Cell-Aware pattern sets for industrial designs , 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.
[21] C. Morandi,et al. Failure modes and mechanisms for VLSI ICs - a review , 1985 .
[22] Jennifer Dworak,et al. When Optimized N-Detect Test Sets are Biased: An Investigation of Cell-Aware-Type Faults and N-Detect Stuck-At ATPG , 2014, 2014 IEEE 23rd North Atlantic Test Workshop.
[23] Fen Chen,et al. Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).
[24] Friedrich Hapke,et al. Defect-oriented cell-internal testing , 2010, 2010 IEEE International Test Conference.
[25] Yehea Ismail,et al. Figures of merit to characterize the importance of on-chip inductance , 1999 .
[26] Friedrich Hapke,et al. DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies , 2018, 2018 IEEE International Test Conference (ITC).
[27] Friedrich Hapke,et al. Cell-aware diagnosis: Defective inmates exposed in their cells , 2016, 2016 21th IEEE European Test Symposium (ETS).
[28] Dnyan Khatri,et al. Simulation assisted uncovering and understanding of complex failures in 28nm microprocessor devices , 2016, 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
[29] Vishwani D. Agrawal,et al. Delay fault models and coverage , 1998, Proceedings Eleventh International Conference on VLSI Design.
[30] Yves Crouzet,et al. Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.
[31] Erik Jan Marinissen,et al. Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults , 2020, 2020 IEEE European Test Symposium (ETS).
[32] Edward J. McCluskey,et al. An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[33] Irith Pomeranz,et al. Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[34] Kees G. W. Goossens,et al. Defect-Location Identification for Cell-Aware Test , 2019, 2019 IEEE Latin American Test Symposium (LATS).
[35] Arvind Jain,et al. Using Cell Aware Diagnostic Patterns to Improve Diagnosis Resolution for Cell Internal Defects , 2017, 2017 IEEE 26th Asian Test Symposium (ATS).
[36] John Paul Shen,et al. Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.