Adaptive simulation-based framework for error characterization of inexact circuits

Abstract To design faster and more energy-efficient systems, numerous inexact arithmetic operators have been proposed, generally obtained by modifying the logic structure of conventional circuits. However, as the quality of service of an application has to be ensured, these operators need to be precisely characterized to be usable in commercial or real-life applications. The characterization of the error induced by inexact operators is commonly achieved with exhaustive or stochastic bit-accurate gate-level simulations. However, for high bit-widths, the time and memory required for such simulations become prohibitive. To overcome these limitations, a new characterization framework for inexact operators is proposed. The proposed framework characterizes the error induced by inexact operators in terms of mean error distance, error rate and maximum error distance, allowing to completely define the error probability mass function. By exploiting statistical properties of the approximation error, the number of simulations needed for precise characterization is minimized. From user-defined confidence requirements, the proposed method computes the minimal number of simulations to obtain the desired accuracy on the characterization for the error rate and mean error distance. The maximum error distance value is then extracted from the simulated samples using the extreme value theory. For 32-bit adders, the proposed method reduces the number of simulations needed up to a few tens of thousands points.

[1]  Muhammad Shafique,et al.  Probabilistic Error Modeling for Approximate Adders , 2017, IEEE Transactions on Computers.

[2]  Tong Liu,et al.  Performance improvement with circuit-level speculation , 2000, MICRO 33.

[3]  Christian C. Enz,et al.  Energy-efficient inexact speculative adder with high performance and accuracy control , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[4]  David Gregg,et al.  A stochastic bitwidth estimation technique for compact and low-power custom processors , 2008, TECS.

[5]  R. R. Kinnison,et al.  Applied extreme value statistics , 1984 .

[6]  Henry Hoffmann,et al.  Quality of service profiling , 2010, 2010 ACM/IEEE 32nd International Conference on Software Engineering.

[7]  Cunxi Yu,et al.  Analyzing Imprecise Adders Using BDDs -- A Case Study , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[8]  Daniel Ménard,et al.  Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits , 2018, 2018 26th European Signal Processing Conference (EUSIPCO).

[9]  Sachin S. Sapatnekar,et al.  An Analytical Approach for Error PMF Characterization in Approximate Circuits , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Christian C. Enz,et al.  A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Peter J. Varman,et al.  High performance reliable variable latency carry select addition , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Yi Wu,et al.  An Accurate and Efficient Method to Calculate the Error Statistics of Block-based Approximate Adders , 2017, ArXiv.

[13]  Avishek Sinha Roy,et al.  A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[14]  Jari Nurmi,et al.  Approximate computing for complexity reduction in timing synchronization , 2014, EURASIP J. Adv. Signal Process..

[15]  Paolo Ienne,et al.  Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.

[16]  Kaushik Roy,et al.  Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Sachin S. Sapatnekar,et al.  SABER: Selection of approximate bits for the design of error tolerant circuits , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[18]  Daniel Ménard,et al.  Dynamic precision scaling for low power WCDMA receiver , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[19]  Maxime Pelcat,et al.  A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing Systems , 2018, ACM Great Lakes Symposium on VLSI.

[20]  R. Lowry,et al.  Concepts and Applications of Inferential Statistics , 2014 .

[21]  Erwan Nogues,et al.  New non-uniform segmentation technique for software function evaluation , 2016, 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[22]  Ramon E. Moore Interval arithmetic and automatic error analysis in digital computing , 1963 .

[23]  John Lach,et al.  A methodology for energy-quality tradeoff using imprecise hardware , 2012, DAC Design Automation Conference 2012.

[24]  Maxime Pelcat,et al.  Smart search space reduction for approximate computing: A low energy HEVC encoder case study , 2017, J. Syst. Archit..

[25]  George A. Constantinides,et al.  Accuracy-Performance Tradeoffs on an FPGA through Overclocking , 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

[26]  Christian Enz,et al.  Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[27]  Fabrizio Lombardi,et al.  An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders , 2015, IEEE Transactions on Computers.

[28]  Fabrizio Lombardi,et al.  A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits , 2017, ACM J. Emerg. Technol. Comput. Syst..

[29]  Gang Wang,et al.  Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.

[30]  Michael Thomas,et al.  Statistical Analysis of Extreme Values , 2008 .