Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C

As designers may model mixed hardware-software systems using a subset of C or C++, we present SpC, a solution to synthesize and optimize hardware C models with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference data mapped to registers, ports, or wires. Pointer analysis is used to find the set of locations each pointer may reference in a program at compile time. In this paper, we address the problem of synthesizing and optimizing pointers to multiple variables or array elements. The value of the pointers are encoded and branching statements are used to dynamically access data referenced by pointers. A heuristic is used to efficiently encode the values of the pointers. Compiler techniques are also used to reduce storage before loads and stores. An implementation using the SUIF framework (Wilson et al., 1994; SUIF Compiler Framework) is presented, followed by some case studies and experimental results.

[1]  Luca Benini,et al.  State assignment for low power dissipation , 1995 .

[2]  Luciano Lavagno,et al.  ECL: a specification environment for system-level design , 1999, DAC '99.

[3]  Luca Benini,et al.  Address bus encoding techniques for system-level power optimization , 1998, Proceedings Design, Automation and Test in Europe.

[4]  Wayne Wolf,et al.  High-Level VLSI Synthesis , 1991 .

[5]  G. De Micheli,et al.  Resolution of dynamic memory allocation and pointers for the behavioral synthesis from C , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[6]  M. Gokhale,et al.  FPGA computing in a data parallel C , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[7]  John Wawrzynek,et al.  Instruction-Level Parallelism for Reconfigurable Computing , 1998, FPL.

[8]  Amer Diwan,et al.  SUIF Explorer: an interactive and interprocedural parallelizer , 1999, PPoPP '99.

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  MUSTANG: state assignment of finite state machines targeting multilevel logic implementations , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Christopher Duff Codage d'automates et théorie des cubes intersectants. (State assignment of finite state machine and intersecting cube theory) , 1991 .

[11]  N.R. Malik,et al.  Graph theory with applications to engineering and computer science , 1975, Proceedings of the IEEE.

[12]  Bjarne Stroustrup,et al.  C++ Programming Language , 1986, IEEE Softw..

[13]  Luciano Lavagno,et al.  ECL: a specification environment for system-level design , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[14]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[15]  Kazutoshi Wakabayashi,et al.  C-based synthesis experiences with a behavior synthesizer, "Cyber" , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[16]  Giovanni De Micheli,et al.  Resolution of dynamic memory allocation and pointers for the behavioral synthesis form C , 2000, DATE '00.

[17]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[18]  Gabriele Saucier,et al.  ASYL: A Rule-Based System for Controller Synthesis , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Gabriele Saucier,et al.  State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory , 1989, 26th ACM/IEEE Design Automation Conference.

[20]  Giovanni De Micheli,et al.  SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C , 1998, ICCAD.

[21]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[22]  Jianwen Zhu,et al.  Specification and Design of Embedded Systems , 1998, Informationstechnik Tech. Inform..

[23]  Giovanni De Micheli,et al.  Memory Representation and Hardware Synthesis of C Code with Pointers and Complex Data Structures , 2003 .

[24]  Giovanni De Micheli Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros , 1986, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Alexandru Nicolau,et al.  Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration , 1998 .

[26]  Monica S. Lam,et al.  Efficient context-sensitive pointer analysis for C programs , 1995, PLDI '95.

[27]  Edward J. McCluskey,et al.  The Coding of Internal States of Sequential Circuits , 1964, IEEE Trans. Electron. Comput..

[28]  C.E. Stroud,et al.  Behavioral model synthesis with Cones , 1988, IEEE Design & Test of Computers.

[29]  Giovanni De Micheli,et al.  High Level Synthesis of ASlCs un - der Timing and Synchronization Constraints , 1992 .

[30]  Chantal Ykman-Couvreur,et al.  Memory management for embedded network applications , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Diederik Verkest,et al.  Hardware/software co-design of digital telecommunication systems , 1997, Proc. IEEE.

[32]  Koichi Nishida,et al.  Hardware synthesis with the Bach system , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[33]  Yanbing Li,et al.  Hardware-software co-design of embedded reconfigurable architectures , 2000, DAC.

[34]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[35]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[36]  Csaba Andras Moritz,et al.  Parallelizing applications into silicon , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[37]  Michael J. Flynn,et al.  PAM-Blox: high performance FPGA design for adaptive computing , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[38]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[39]  Stan Y. Liao,et al.  An efficient implementation of reactivity for modeling hardware in the scenic design environment , 1997, DAC.

[40]  Gabriele Saucier State Assignment of Asynchronous Sequential Machines Using Graph Techniques , 1972, IEEE Transactions on Computers.

[41]  Giovanni De Micheli,et al.  Encoding of Pointers for Hardware Synthesis , 1998 .

[42]  Ephraim Feig,et al.  New scaled DCT algorithms for fused multiply/add architectures , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[43]  Patrick Schaumont,et al.  A programming environment for the design of complex high speed ASICs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[44]  Francky Catthoor,et al.  Custom Memory Management Methodology , 1998, Springer US.

[45]  Steven W. K. Tjiang,et al.  SUIF: an infrastructure for research on parallelizing and optimizing compilers , 1994, SIGP.

[46]  Martin C. Rinard,et al.  Pointer analysis for multithreaded programs , 1999, PLDI '99.

[47]  Bjarne Steensgaard Points-to Analysis by Type Inference of Programs with Structures and Unions , 1996, CC.

[48]  Jörg Henkel,et al.  The COSYMA environment for hardware/software cosynthesis of small embedded systems , 1996, Microprocess. Microsystems.

[49]  Stan Y. Liao,et al.  Hardware synthesis from C/C++ , 1999, DATE '99.

[50]  Tiziano Villa,et al.  Theory and algorithms for face hypercube embedding , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[51]  Stan Y. Liao Towards a new standard for system-level design , 2000, CODES '00.